參數(shù)資料
型號(hào)： MB90F922NCPMC
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER, PQFP120
封裝： 16 X 16 MM, 1.70 MM HEIGHT, 0.50 M PITCH, PLASTIC, LQFP-120
文件頁(yè)數(shù)： 44/72頁(yè)
文件大?。?/td> 2151K
代理商： MB90F922NCPMC
MB90920 Series
DS07-13750-3E
49
(Continued)
*1 : When the PLL multiplier is
× 1, × 2, × 3 or × 4 and the internal clock is 20 MHz < fCP ≤ 32 MHz, set
DIV2 bit
= “1”*4, CS2 bit = “1” in the PSCCR register.
[Example] When using a base oscillator frequency of 24 MHz at PLL
× 1 :
CKSCR register : CS1 bit
= “0”, CS0 bit = “0”
PSCCR register : DIV2 bit
= “1”*4 ,CS2 bit = “1”
[Example] When using a base oscillator frequency of 6 MHz at PLL
× 3 :
CKSCR register : CS1 bit
= “1”, CS0 bit = “0”
PSCCR register : DIV2 bit
= “1”*4 , CS2 bit = “1”
*2 : When the PLL multiplier is
× 2 or × 4 and the internal clock is 20 MHz < fCP ≤ 32 MHz, the following
settings are also supported.
PLL
× 2 : CKSCR register : CS1 bit = “0”, CS0 bit = “0”
PSCCR register : DIV2 bit
= “0”*4 ,CS2 bit = “0”
PLL
× 4 : CKSCR register : CS1 bit = “0”, CS0 bit = “1”
PSCCR register : DIV2 bit
= “0”*4 ,CS2 bit = “0”
*3 : When the PLL multiplier is set to
× 6 or × 8 set “DIV2 bit = “0”*4 CS2 bit = “1”
and “PLL2 bit
= 1” in the PSCCR register.
[Example] When using a base oscillator frequency of 4 MHz at PLL
× 6 :
CKSCR register : CS1 bit
= “1”, CS0 bit = “0”
PLLOS register : DIV2 bit
= “0”*4 ,CS2 bit = “1”
[Example] When using a base oscillator frequency of 3 MHz at PLL
× 8 :
CKSCR register : CS1 bit
= “1”, CS0 bit = “1”
PLLOS register : DIV2 bit
= “0”*4 ,CS2 bit = “1”
*4 : The DIV2 bit is assigned to bit 9 of the PSCCR register and the CS2 bit is assigned to bit 8 of the PSCCR
register. Both bits have a default value of “0”.
32
No multiplier
25
24
20
18
16
12
9
8
6
4
1.5
3 56 8 10 12.5 16
20
25
32
4
x 3*1
x 6*3
x 4
*1,*2
x 2*1,*2
x 1*1
x 8*3
Base oscillator frequency vs. Internal operating clock frequency
Base oscillator clock FCP (MHz)
Internal
clock
f
CP
(MHz)
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