參數(shù)資料
型號(hào)： MB90F912BSPMC
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 32 MHz, MICROCONTROLLER, PQFP48
封裝： 7 X 7 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-48
文件頁(yè)數(shù)： 34/64頁(yè)
文件大?。?/td> 1749K
代理商： MB90F912BSPMC
MB90910 Series
4
DS07–13755–2E
■ PRODUCT LINEUP
(Continued)
Part number
Parameter
MB90V950AMAS
MB90F912BS
MB90911AS
Type
Evaluation product
Flash memory product
MASK ROM product
CPU
F2MC-16LX CPU
System clock
On-chip PLL clock multiplier (
×1, ×2, ×3, ×4, ×6, ×8, 1/2 when PLL stops)
Minimum instruction execution time : 31.25 ns (4 MHz osc. PLL
×8)
ROM
External
128 Kbytes
64 Kbytes
RAM
30 Kbytes
8 Kbytes
4 Kbytes
Emulator-specific
power supply*1
Yes
FPGA data*2
Rev 050617
Adaptor board*2
MB2147-20 Rev.04C or later
Technology
0.35
μm CMOS with built-in
power supply regulator
0.18
μm CMOS with built-in power supply regulator
Operation voltage
range
5 V
± 10 %
3.0 V to 5.5 V : When normal operating
Operating ambient
temperature
40 °C to +105 °C
Package
PGA-299
LQFP-48
UART
LIN-UART
× 7 channels
LIN-UART
× 2 channels, UART × 1 channel
Wide range of baud rate settings using a dedicated reload timer
Special synchronous options for adapting to different synchronous serial protocols
LIN functionality working either as master or slave LIN device (Supported by LIN-UART
only)
I2C (400 kbps)
2 channels
A/D converter
24 input channels
16 input channels
10-bit or 8-bit resolution
Conversion time : Min 3
μs include sample time (per one channel)
16-bit
Reload timer
4 channels
2 channels
Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys
= Machine clock frequency)
Supports External Event Count function
16-bit
I/O timer
2 channels
1 channel
Generates an interrupt signal on overflow
Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27
(fsys
= Machine clock freq.)
I/O Timer 0 (clock input FRCK0) corresponds to ICU0/1/2/3, OCU 0/1/2/3
I/O Timer 1 (clock input FRCK1) corresponds to ICU4/5/6/7, OCU 4/5/6/7
16-bit
Output compare
8 channels
Generates an interrupt signal when one of the 16-bit I/O timer matches the output com-
pare register
A pair of compare registers can be used to generate an output signal.
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