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參數(shù)資料
| 型號： | MB90F897YPMT |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP48 |
| 封裝： | 0.50 MM PITCH, PLASTIC, LQFP-48 |
| 文件頁數(shù)： | 1/52頁 |
| 文件大?。?/td> | 1370K |
| 代理商： | MB90F897YPMT |
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FUJITSU MICROELECTRONICS
DATA SHEET
Copyright2004-2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2009.8
For the information for microcontroller supports, see the following web site.
This web site includes the "Customer Design Review Supplement" which provides the latest cautions on
system development and the minimal requirements to be checked to prevent problems before the system
development.
http://edevice.fujitsu.com/micom/en-support/
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90895 Series
MB90F897/F897S/F897Y*1/F897YS*1/
MB90V495G
■ DESCRIPTION
MB90895 series devices are 16-bit general-purpose microcontrollers designed for applications which need high-
speed real-time processing. The devices of this series are high-performance 16-bit CPU microcontrollers em-
ploying of the dual operation flash memory and CAN controller on LQFP-48 small package.
The system, inheriting the architecture of F2MC*2 family, employs additional instruction ready for high-level lan-
guages, expanded addressing mode, enhanced multiply-divide instructions, and enriched bit-processing instruc-
tions. Furthermore, employment of 32-bit accumulator achieves processing of long-word data (32 bits).
The peripheral resources of MB90895 series include the following:
8/10-bit A/D converter, UART0/UART1 (SCI), 8/16-bit PPG timer, 16-bit input-output timer (16-bit free-run timer,
input capture 0, 1, 2, 3 (ICU)), and CAN controller.
*1 : These devices are under development. This datasheet provides preliminary information for the devices under
development.
*2 : “F2MC” is the abbreviation of FUJITSU Flexible Microcontroller.
■ FEATURES
Models that support +125°C (MB90F897/S)
Models that support +150°C (MB90F897Y/YS)
Clock
Built-in PLL clock frequency multiplication circuit
Selection of machine clocks (PLL clocks) is allowed among frequency division by two on oscillation clock, and
multiplication of 1 to 4 times of oscillation clock (for 4-MHz oscillation clock, 4 MHz to 16 MHz).
Operation by sub-clock (8.192 kHz) is allowed. (MB90F897/Y)
Minimum execution time of instruction: 62.5 ns (when operating with 4-MHz oscillation clock, and 4-time multi-
plied PLL clock).
16 Mbyte CPU memory space
24-bit internal addressing
(Continued)
DS07-13731-5E
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