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參數(shù)資料
| 型號： | MB90F804 |
| 廠商： | Fujitsu Limited |
| 英文描述： | 16-bit Proprietary Microcontroller CMOS |
| 中文描述： | 16位微控制器專有的CMOS |
| 文件頁數(shù)： | 24/88頁 |
| 文件大?。?/td> | 385K |
| 代理商： | MB90F804 |
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MB90800 Series
24
I
INTERRUPT SOURCES, INTERRUPT VECTORS AND INTERRUPT CONTROL REGISTERS
: Available
×
: Unavailable
: Available El
2
OS function is provided.
: Available when a cause of interrupt sharing a same ICR is not used.
* : When interrupts of the same level are output at the same time, the interrupt with the smallest interrupt vector
number has the priority.
When there are two interrupt causes in the same interrupt control register (ICR) and use of IIOS is enabled,
IIOS is started upon detection of one of the interrupt causes. As interrupts other than the start cause are
masked during IIOS start, masking one of the interrupt requests is recommended when using IIOS.
For a resource that has two interrupt causes in the same interrupt control register (ICR), the interrupt flag is
cleared by an IIOS interrupt clear signal.
Interrupt source
EI
2
OS
readiness
Interrupt vector
Number*
#08
08
H
#09
09
H
#10
0A
H
#11
0B
H
#13
0D
H
#15
0F
H
#16
10
H
#17
11
H
#18
12
H
#19
13
H
#21
15
H
#23
17
H
#24
18
H
#25
19
H
#26
1A
H
#27
1B
H
#29
1D
H
#31
1F
H
#33
21
H
#35
23
H
#36
24
H
#37
25
H
#38
26
H
#39
27
H
#40
28
H
#41
29
H
#42
2A
H
Interrupt control register
ICR
ICR00
ICR01
Priority
Address
FFFFDC
H
FFFFD8
H
FFFFD4
H
FFFFD0
H
FFFFC8
H
FFFFC0
H
FFFFBC
H
FFFFB8
H
FFFFB4
H
FFFFB0
H
FFFFA8
H
FFFFA0
H
FFFF9C
H
FFFF98
H
FFFF94
H
FFFF90
H
FFFF88
H
FFFF80
H
FFFF78
H
FFFF70
H
FFFF6C
H
FFFF68
H
FFFF64
H
FFFF60
H
FFFF5C
H
FFFF58
H
FFFF54
H
Address
0000B0
H
0000B1
H
Reset
INT 9 instruction
Exceptional treatment
DTP/External interrupt ch0
DTP/External interrupt ch1
Serial I/O ch2
DTP/External interrupt ch2/3
Serial I/O ch3
16-bit free-run timer
Watch timer
16-Bit Reload Timer ch2
16-Bit Reload Timer ch0
16-Bit Reload Timer ch1
Input capture ch0
Input capture ch1
PPG timer ch0 counter-borrow
Output compare match
PPG timer ch1 counter-borrow
Time-base timer
UART0 reception end
UART0 transmission end
A/D converter conversion termination
I
2
C Interface
UART1 : Reception
UART1 : Transmission
Flash memory status
Delayed interrupt output module
×
×
×
High
×
ICR02
0000B2
H
×
ICR03
0000B3
H
×
ICR04
ICR05
0000B4
H
0000B5
H
ICR06
0000B6
H
ICR07
0000B7
H
ICR08
ICR09
ICR10
ICR11
0000B8
H
0000B9
H
0000BA
H
0000BB
H
×
ICR12
0000BC
H
ICR13
0000BD
H
×
ICR14
0000BE
H
×
×
ICR15
0000BF
H
Low
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