參數(shù)資料
型號： MB90F568PMC
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP64
封裝： 12 X 12 MM, 1.70 MM HEIGHT, 0.65 MM PITCH, PLASTIC, LQFP-64
文件頁數(shù)： 33/92頁
文件大小： 2097K
代理商： MB90F568PMC
MB90560/565 Series
DS07-13715-5E
39
An interrupt can be generated when an active edge is detected on the external signal (ICS01, ICS23 : ICE0
= “1”, ICE1 = “1”, ICE2 = “1”, ICE3 = “1”) .
8/16-bit PPG timer (8-bit : 6 channels, 16-bit : 3 channels)
The 8/16-bit PPG timer consists of an 8-bit down counter (PCNT) , PPG control registers (PPGC0 to PPGC
5) , PPG clock control registers (PCS01, PCS23, PCS45) , and PPG reload registers (PRLL0 to PRLL5, PRLH0
to PRLH5) .
When used as an 8/16-bit reload timer, the PPG operates as an event timer. The PPG can also be used to output
pulses with specified frequency and duty ratio.
8-bit PPG mode
Each channel operates as an independent 8-bit PPG.
8-bit prescaler
+ 8-bit PPG mode
ch0 (ch2, ch4) operates as an 8-bit prescaler and ch1 (ch3, ch5) operates as a variable frequency PPG by
counting up on the borrow output from ch0 (ch2, ch4) .
16-bit PPG mode
ch0 (ch2, ch4) and ch1 (ch3, ch5) operate together as a 16-bit PPG.
PPG operation
Outputs pulses with the specified frequency and duty ratio (ratio of “H” level period and “L” level period), and
can also be used as a D/A converter when combined with an external circuit.
Waveform generator
The waveform generator consists of an 8-bit timer, 8-bit timer control registers (DTCR0 to DTCR2) , 8-bit reload
registers (TMRR0 to TMRR2) , and waveform control register (SIGCR) .
The waveform generator can generate a DC chopper output or non-overlapping three-phase waveform output
for inverter control using the realtime outputs (RT0 to RT5) and 8/16-bit PPG timer.
A non-overlapping waveform can be generated by using the 8-bit timer as a deadtime timer and adding a non-
overlap time delay to the PPG timer pulse output. (Deadtime timer function)
A non-overlapping waveform can be generated by using the 8-bit timer as a deadtime timer and adding a non-
overlap time delay to the realtime outputs (RT1, RT3, RT5) . (Deadtime timer function)
A GATE signal can be generated when a match occurs between the count from the 16-bit freerun timer and
compare register in the output compare (OCCP0 to OCCP5) (rising edge on realtime output (RT) ) to control
the PPG timer operation. (GATE function)
Can control the RTO0 to RTO5 pin outputs using the DTTI pin input.
By making the DTTI pin input clockless, the pins can be controlled externally even when the oscillation clock
is halted. (The level for each pin can be set by the program.) However, the I/O ports (P30 to P35) must have
been set beforehand as outputs and the output values set in the port 3 data register (PDR3) .
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