參數(shù)資料
型號: MB90F523BPFV
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: Octal Edge-Triggered D-type Flip-Flops With 3-State Outputs 20-CDIP -55 to 125
中文描述: 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP120
封裝: 20 X 20 MM, 3.85 MM HEIGHT, 0.50 MM PITCH, PLASTIC, QFP-120
文件頁數(shù): 70/99頁
文件大小: 978K
代理商: MB90F523BPFV
MB90520A/520B Series
70
18. Address Match Detection Function
If the program address during program execution matches the value set in one of the detection address setting
registers (PADR) , the address match detection function replaces the instruction being executed with the INT9
instruction and executes the interrupt handler program.
The address match detection function provides a simple method of correcting programming errors (patching)
using RAM or similar.
Address match detection functions
Block diagram
Function
No. of address settings
Two channels (two addresses can be set)
An interrupt is generated when the program address matches the detection
address setting register.
Not supported by the extended intelligent I/O service (EI
2
OS) .
Interrupts
EI
2
OS support
ADE1
Reserved Reserved Reserved Reserved
ADD1
ADE0
ADD0
PADR1 (24 bit)
PADR0 (24 bit)
Address latch
PACSR
I
Detection address setting register
Detection address setting register
Address detection control register (PACSR)
C
INT9 instruction
(generates an INT9 interrupt)
Reserved : Always set to “0”.
相關(guān)PDF資料
PDF描述
MB90V520 16-bit Proprietary Microcontroller
MB90522 36-Bit Bus Transceivers With 3-State Outputs 100-LQFP -55 to 125
MB90522PFF Quadruple 2-Input Positive-NAND Gates 14-CDIP -55 to 125
MB90522PFV Quadruple 2-Input Positive-NAND Gates 14-CFP -55 to 125
MB90523 Quadruple 2-Input Positive-NAND Gates 20-LCCC -55 to 125
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