參數(shù)資料
型號(hào)： MB90F523BPFV
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： Octal Edge-Triggered D-type Flip-Flops With 3-State Outputs 20-CDIP -55 to 125
中文描述： 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP120
封裝： 20 X 20 MM, 3.85 MM HEIGHT, 0.50 MM PITCH, PLASTIC, QFP-120
文件頁數(shù)： 27/99頁
文件大?。?/td> 978K
代理商： MB90F523BPFV
MB90520A/520B Series
27
(Continued)
Initial value notation
0
: Initial value of bit is “0”.
1
: Initial value of bit is “1”.
X
: Initial value of bit is undefined.
*1 : Access is prohibited to the address range 0000C0
H
to 0000FF
H
. See the “
I
MEMORY MAP” section.
*2 : See the “
I
MEMORY MAP” section for details of the “ (RAM area) ”.
*3 : “ (Reserved areas) ” are addresses used internally by the system and may not be used.
*4 : The “ (Area reserved for system use) ” contains setting registers used by the evaluation tools.
Notes :
LPMCR, CKSCR, and WDTC are initialized by some types of reset and not by others. The initial values
listed are for the case when the registers are initialized.
The boundary address “####
H
” between the “ (RAM area) ” and “ (Reserved area) ” differs depending on
the product. See the “
I
MEMORY MAP” section for details.
OCU compare registers ch.0 to ch.3 use 16-bit freerun timer 0 and OCU compare registers ch.4 to ch.7
use 16-bit freerun timer 1. Note that 16-bit freerun timer 0 is also used by input capture 0 and 1 (ICU) .
Address
Abbreviated
Register
Name
Register Name
Peripheral Name
Initial Value
0000BE
H
ICR14
Interrupt control register 14
Interrupt controller
0
0
0
0
0
1
1
1
B
0000BF
H
ICR15
Interrupt control register 15
0
0
0
0
0
1
1
1
B
0000C0
H
to
0000FF
H
(Access prohibited)
*1
000100
H
to
00####
H
(RAM area)
*2
00####
H
to
001FEF
H
(Reserved area)
*3
001FF0
H
PADR0
Detection address setting register 0
(low byte)
Address match
detection function
XXXXXXXX
B
001FF1
H
Detection address setting register 0
(middle byte)
XXXXXXXX
B
001FF2
H
Detection address setting register 0
(high byte)
XXXXXXXX
B
001FF3
H
PADR1
Detection address setting register 1
(low byte)
XXXXXXXX
B
001FF4
H
Detection address setting register 1
(middle byte)
XXXXXXXX
B
001FF5
H
Detection address setting register 1
(high byte)
XXXXXXXX
B
001FF6
H
to
001FFF
H
(Reserved area)
*3
相關(guān)PDF資料
PDF描述
MB90V520 16-bit Proprietary Microcontroller
MB90522 36-Bit Bus Transceivers With 3-State Outputs 100-LQFP -55 to 125
MB90522PFF Quadruple 2-Input Positive-NAND Gates 14-CDIP -55 to 125
MB90522PFV Quadruple 2-Input Positive-NAND Gates 14-CFP -55 to 125
MB90523 Quadruple 2-Input Positive-NAND Gates 20-LCCC -55 to 125
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