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參數(shù)資料
| 型號： | MB90F463APMC |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | 12 X 12 MM, 1.70 MM HEIGHT, 0.65 MM PITCH, PLASTIC, LFQFP-64 |
| 文件頁數(shù)： | 22/88頁 |
| 文件大?。?/td> | 2202K |
| 代理商： | MB90F463APMC |
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MB90460/465 Series
DS07-13714-2E
29
(Continued)
: Can be used and support the EI2OS stop request.
: Can be used and interrupt request flag is cleared by EI2OS interrupt clear signal.
: Cannot be used.
: Usable when an interrupt cause that shares the ICR is not used.
*1: - For peripheral functions that share the ICR register, the interrupt level will be the same.
- If the extended intelligent I/O service is to be used with a peripheral function that shares the ICR register with
another peripheral function, the service can be started by either of the function. And if EI2OS clear is supported,
both interrupt request flags for the two interrupt causes are cleared by EI2OS interrupt clear signal. It is recom-
mended to mask either of the interrupt request during the use of EI2OS.
- EI2OS service cannot be started multiple times simultaneously. Interrupt other than the operating interrupt is
masked during EI2OS operation. It is recommended to mask either of the interrupt requests during the use of
EI2OS.
*2: This priority is applied when interrupts of the same level occur simultaneously.
*3: In MB90465 series, these resources are not present, and therefore the interrupts are not available.
Interrupt cause
EI2OS
support
Interrupt vector
Interrupt control
register
Priority
*2
Number
Address
ICR
Address
Input capture channels 2/3
#35
23H
FFFF70H
ICR12 0000BCH*1
Timebase timer
#36
24H
FFFF6CH
UART1 receive
#37
25H
FFFF68H
ICR13 0000BDH*1
UART1 send
#38
26H
FFFF64H
UART0 receive
#39
27H
FFFF60H
ICR14 0000BEH*1
UART0 send
#40
28H
FFFF5CH
Flash memory status
#41
29H
FFFF58H
ICR15
0000BFH*1
Delayed interrupt generator module
#42
2AH
FFFF54H
Low
×
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