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參數(shù)資料
| 型號： | MB90F457SPMT |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Octal Registered Transceiver With 3-State Outputs 24-CDIP -55 to 125 |
| 中文描述： | 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP48 |
| 封裝： | 7 X 7 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-48 |
| 文件頁數(shù)： | 50/78頁 |
| 文件大?。?/td> | 680K |
| 代理商： | MB90F457SPMT |
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MB90455 Series
50
12. Address Matching Detection Function Outline
The address matching detection function checks if an address of an instruction to be processed next to a currently-
processed instruction is identical with an address specified in the detection address register. If the addresses
match with each other, an instruction to be processed next in program is forcibly replaced with INT9 instruction,
and process branches to the interrupt process program. Using INT9 interrupt, this function is available for
correcting program by batch processing.
Address matching detection function outline
An address of an instruction to be processed next to a currently-processed instruction of the program is always
retained in an address latch via internal data bus. By the address matching detection function, the address
value retained in the address latch is always compared with an address specified in detection address setting
register. If the compared address values match with each other, an instruction to be processed next by CPU
is forcibly replaced with INT9 instruction, and an interrupt process program is executed.
Two detection address setting registers are provided (PADR0 and PADR1), and each register is provided with
interrupt permission bit. Generation of interrupt, which is caused by address matching between the address
retained in address latch and the address specified in address setting register, is permitted and prohibited on
a register-by-register basis.
Address matching detection function block diagram
Address latch
Retains address value output to internal data bus.
Address detection control register (PACSR)
Specifies if interrupt is permitted or prohibited when addresses match with each other.
Detection address setting (PADR0, PADR1)
Specifies addresses to be compared with values in address latch.
PADR0
24bit
AD1E
AD0E
PACSR
PADR1
24bit
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Address latch
Detection address setting register 0
Detection address setting register 1
INT9 instruction
(generate INT9 interrupt)
Address detection control register (PACSR)
Reserved: Be sure to set to “0.”
I
C
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