MB90420G/5G (A) Series
82
Table 7
Transfer Instructions (Byte) [41 Instructions]
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
Mnemonic
#
~
RG
B
Operation
LH AH
I
S
T
N
Z
V
C
RMW
MOV
A, dir
MOV
A, addr16
MOV
A, Ri
MOV
A, ear
MOV
A, eam
MOV
A, io
MOV
A, #imm8
MOV
A, @A
MOV
A, @RLi+disp8
MOVN A, #imm4
MOVX
A, dir
MOVX
A, addr16
MOVX
A, Ri
MOVX
A, ear
MOVX
A, eam
MOVX
A, io
MOVX
A, #imm8
MOVX
A, @A
MOVX
A,@RWi+disp8
MOVX
A, @RLi+disp8
MOV
dir, A
MOV
addr16, A
MOV
Ri, A
MOV
ear, A
MOV
eam, A
MOV
io, A
MOV
@RLi+disp8, A
MOV
Ri, ear
MOV
Ri, eam
MOV
ear, Ri
MOV
eam, Ri
MOV
Ri, #imm8
MOV
io, #imm8
MOV
dir, #imm8
MOV
ear, #imm8
MOV
eam, #imm8
MOV
@AL, AH
/MOV
@A, T
XCH
A, ear
XCH
A, eam
XCH
Ri, ear
XCH
Ri, eam
2
3
1
2
2+
2
3
1
2
3
2
2+
2
3
2
3
1
2
2+
2
3
2
2+
2
2+
2
3
3+
2
2+
2
2+
3
4
2
3+ (a)
3
2
3
10
1
3
4
2
3+ (a)
3
2
3
5
10
3
4
2
3+ (a)
3
10
3
4+ (a)
4
5+ (a)
2
5
2
4+ (a)
3
4
5+ (a)
7
9+ (a)
0
1
0
2
0
1
0
1
2
0
1
0
2
1
2
1
0
1
0
2
0
4
2
(b)
0
(b)
0
(b)
0
(b)
0
(b)
0
(b)
0
(b)
0
(b)
0
(b)
0
(b)
0
(b)
0
2
× (b)
0
2
× (b)
byte (A)
← (dir)
byte (A)
← (addr16)
byte (A)
← (Ri)
byte (A)
← (ear)
byte (A)
← (eam)
byte (A)
← (io)
byte (A)
← imm8
byte (A)
← ((A))
byte (A)
← ((RLi)+disp8)
byte (A)
← imm4
byte (A)
← (dir)
byte (A)
← (addr16)
byte (A)
← (Ri)
byte (A)
← (ear)
byte (A)
← (eam)
byte (A)
← (io)
byte (A)
← imm8
byte (A)
← ((A))
byte (A)
← ((RWi)+disp8)
byte (A)
← ((RLi)+disp8)
byte (dir)
← (A)
byte (addr16)
← (A)
byte (Ri)
← (A)
byte (ear)
← (A)
byte (eam)
← (A)
byte (io)
← (A)
byte ((RLi) +disp8)
← (A)
byte (Ri)
← (ear)
byte (Ri)
← (eam)
byte (ear)
← (Ri)
byte (eam)
← (Ri)
byte (Ri)
← imm8
byte (io)
← imm8
byte (dir)
← imm8
byte (ear)
← imm8
byte (eam)
← imm8
byte ((A))
← (AH)
byte (A)
(ear)
byte (A)
(eam)
byte (Ri)
(ear)
byte (Ri)
(eam)
Z
X
–
Z
–
*
–
*
–
*
–
*
R
*
–
*
–
*
–
*
–
*
–
*
–