參數(shù)資料
型號： MB90F394HPMT
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 16-bit Proprietary Microcontroller CMOS
中文描述： 16-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQFP120
封裝： 16 X 16 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-120
文件頁數(shù)： 29/61頁
文件大?。?/td> 317K
代理商： MB90F394HPMT
MB90390 Series
29
(Continued)
Address
Register
Abbrevia-
tion
Access
Resource name
Initial value
35AB
H
I
2
C Clock Control Register
ICCR
R/W
I
2
C Interface
X0011111
35AC
H
to
35BF
H
Reserved
35C0
H
Parameter Register Low Byte
CMPRL
R/W
Clock Modulator
11111101
35C1
H
Parameter Register High Byte
CMPRH
R/W
XX000010
35C2
H
Clock Modulator Control Register
CMCR
R/W
00010000
35C3
H
to
35C8
H
Reserved
35C9
H
Input Capture Edge 0/1
ICE01
R/W
Input Capture 0/1
XXXXX0XX
35CA
H
Input Capture Edge 2/3
ICE23
R
Input Capture 2/3
XXXXXXXX
35CB
H
Input Capture Edge 4/5
ICE45
R/W
Input Capture 4/5
XXXXX0XX
35CC
H
to
35DF
H
Reserved
35E0
H
Detection Address Setting Register 0
(Low-order)
PADR0
R/W
Address Maching
Detection Function 0
XXXXXXXX
35E1
H
Detection Address Setting Register 0
(Middle-order)
PADR0
R/W
XXXXXXXX
35E2
H
Detection Address Setting Register 0
(High-order)
PADR0
R/W
XXXXXXXX
35E3
H
Detection Address Setting Register 1
(Low-order)
PADR1
R/W
XXXXXXXX
35E4
H
Detection Address Setting Register 1
(Middle-order)
PADR1
R/W
XXXXXXXX
35E5
H
Detection Address Setting Register 1
(High-order)
PADR1
R/W
XXXXXXXX
35E6
H
to
35EF
H
Reserved
35F0
H
Detection Address Setting Register 3
(Low-order)
PADR3
R/W
Address Maching
Detection Function 1
XXXXXXXX
35F1
H
Detection Address Setting Register 3
(Middle-order)
PADR3
R/W
XXXXXXXX
35F2
H
Detection Address Setting Register 3
(High-order)
PADR3
R/W
XXXXXXXX
35F3
H
Detection Address Setting Register 4
(Low-order)
PADR4
R/W
XXXXXXXX
35F4
H
Detection Address Setting Register 4
(Middle-order)
PADR4
R/W
XXXXXXXX
35F5
H
Detection Address Setting Register 4
(High-order)
PADR4
R/W
XXXXXXXX
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