參數(shù)資料
型號： MB90F377PFF-G
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 16-bit Proprietary Microcontroller
中文描述： 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP144
封裝： 0.40 MM PITCH, PLASTIC, LQFP-144
文件頁數(shù)： 60/140頁
文件大?。?/td> 650K
代理商： MB90F377PFF-G
MB90370/375 Series
60
7.
16-bit reload timer (
×
4)
The 16-bit reload timer provides two operating modes, internal clock mode and event count mode. In each
operating mode, the 16-bit down counter can be reloaded (reload mode) or stopped when underflow (one-shot
mode) .
Output pins TO1 to TO4 are able to output different waveform according to the counter operating mode. TO1 to
TO4 toggles when counter underflow if counter is operated as reload mode. TO1 to TO4 output specified level
(“H” or “L”) when counter is counting if the counter is in one-shot mode.
Features of the 16-bit reload timer :
Interrupt generated when timer underflow
EI
2
OS supported
Internal clock operating mode :
Three internal count clocks can be selected.
Counter can be activated by software or external trigger (signal at TIN1 to TIN4 pin) .
Counter can be reloaded or stopped when underflow after activated.
Event count operating mode :
Counter counts down by one when specified edge at TIN1 to TIN4 pin.
Counter can be reloaded or stopped when underflow.
(1) Register configuration of reload timer
Timer Control Status Register (Upper)
Address : ch1
ch2
ch3
ch4
00007D
H
Read/write
Initial value
Timer Control Status Register (Lower)
Address : ch1
ch2
ch3
ch4
00007C
H
Read/write
Initial value
16-bit Timer Register
/
16-bit Reload Register (Upper)
Address : ch1
ch2
ch3
ch4
00007F
H
Read/write
Initial value
16-bit Timer Register
/
16-bit Reload Register (Lower)
Address : ch1
ch2
ch3
ch4
00007E
H
Read/write
Initial value
000071
H
000075
H
000079
H
Bit number
TMCSRH1 to
TMCSRH4
000070
H
000074
H
000078
H
Bit number
TMCSRL1 to
TMCSRL4
000073
H
000077
H
00007B
H
Bit number
TMR1 to TMR4/
TMRD1 to
TMRD4
000072
H
000076
H
00007A
H
Bit number
TMR1 to TMR4/
TMRD1 to
TMRD4
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
CSL1
CSL0
MOD2
MOD1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
2
1
0
OUTE
R/W
0
MOD0
OUTL
RELD
INTE
UF
CNTE
TRG
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
15
14
13
12
11
10
9
8
D14
R/W
X
D15
D13
D12
D11
D10
D09
D08
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
7
6
5
4
3
2
1
0
D06
R/W
X
D07
D05
D04
D03
D02
D01
D00
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