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參數(shù)資料
| 型號： | MB90F356TE |
| 廠商： | Fujitsu Limited |
| 英文描述： | 16-bit Proprietary Microcontrollers |
| 中文描述： | 16位微控制器專有 |
| 文件頁數(shù)： | 27/85頁 |
| 文件大?。?/td> | 880K |
| 代理商： | MB90F356TE |
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MB90350E Series
27
18. Low voltage/CPU operation reset circuit
The low voltage detection reset circuit is a function that monitors power supply voltage in order to detect when
a voltage drops below a given voltage level. When a low voltage condition is detected, an internal reset signal
is generated.
The CPU operation detection reset circuit is a 20-bit counter that uses oscillation as a count clock and generates
an internal reset signal if not cleared within a given time after startup.
(1) Low voltage detection reset circuit
When a low voltage condition is detected, the low voltage detection flag (LVRC : LVRF) is set to “1” and an
internal reset signal is output.
Because the low voltage detection reset circuit continues to operate even in stop mode, detection of a low voltage
condition generates an internal reset and releases stop mode.
During an internal RAM write cycle, low voltage reset is generated after the completion of writing. During the
output of this internal reset, the reset output from the low voltage detection reset circuit is suppressed.
(2) CPU operation detection reset circuit
The CPU operation detection reset circuit is a counter that prevents program runaway. The counter starts
automatically after a power-on reset, and must be continually and regularly cleared within a given time. If the
given time interval elapses and the counter has not been cleared, a cause such as infinite program looping is
assumed and an internal reset signal is generated. The internal reset generated from the CPU operation detection
circuit has a width of 5 machine cycles.
Interval time
* : This value assumes the interval time at an oscillation clock frequency of 4 MHz.
During recovery from standby mode, the detection period is the maximum interval plus 20
μ
s.
This circuit does not operate in modes where CPU operation is stopped.
The CPU operation detection reset circuit counter is cleared under any of the following conditions.
“0” writing to CL bit of LVRC register
Internal reset
Main oscillation clock stop
Transit to sleep mode
Transit to timebase timer mode and watch mode
19. Internal CR oscillation circuit
Detection voltage
4.0 V
±
0.3 V
2
20
/F
C
(approx. 262 ms*)
Parameter
Symbol
Value
Unit
Min
Typ
Max
Oscillation frequency
f
RC
50
100
200
kHz
Oscillation stabilization
wait time
tstab
100
μ
s
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| MB90F362ESPMCR-GE1 | 制造商:FUJITSU 功能描述: |
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| MB90F362TESPMCR-G-JNE1 | 制造商:FUJITSU 功能描述: |
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