參數(shù)資料
型號： MB90F334APMC
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 16-bit Proprietary Microcontroller
中文描述： 16-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQFP120
封裝： 16 X 16 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LFQFP-120
文件頁數(shù)： 72/116頁
文件大?。?/td> 632K
代理商： MB90F334APMC
MB90330 Series
72
13. DTP/External interrupt circuit
DTP (Data Transfer Peripheral)/External interrupt circuit detects the interrupt request input from the external
interrupt input terminal (INT7 to INT0) , and outputs the interrupt request.
DTP/External interrupt circuit function
The DTP/External interrupt function outputs an interrupt request upon detection of the edge or level signal input
to the external interrupt input pins (INT7 to INT0).
If CPU accepts the interrupt request, and if the extended intelligent I/O service (EI
2
OS) is enabled, branches to
the interrupt handling routine after completing the automatic data transfer (DTP function) performed by EI
2
OS.
And if EI
2
OS is disabled, it branches to the interrupt handling routine without activating the automatic data transfer
(DTP function) performed by EI
2
OS.
Overview of DTP/External interrupt circuit
External interrupt
DTP function
Input pin
8 channels (P60/INT0, P61/INT1, P62/INT2/SIN, P63/INT3/SOT, P64/INT4/SCK,
P65/INT5/PWC, P66/INT6/SCL0, P67/INT7/SDA0)
Interrupt source
The detection level or the type of the edge for each terminal can be set in the
request level setting register (ELVR).
Input of H level/L level/rising edge/falling edge.
Interrupt number
#18 (12
H
), #20 (14
H
), #22 (16
H
), #24 (18
H
)
Interrupt control
Enabling/disabling the interrupt request output using the DTP/interrupt enable
register (ENIR)
Interrupt flag
Holding the interrupt causes using the DTP/interrupt cause register (EIRR)
Process setting
Disable EI
2
OS (ICR: ISE=“0”)
Enable EI
2
OS (ICR: ISE=“1”)
Process
Branched to the interrupt handling
routine
After an automatic data transfer by
EI
2
OS, branched to the interrupt
handling routine
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