
MB90330 Series
26
(Continued)
Address
Register
abbreviation
Register
Read/
Write
R/W
R/W
R/W
R/W
R/W
R/W
Resource name
Initial Value
000086
H
000087
H
000088
H
000089
H
00008A
H
00008B
H
00008C
H
to
00009A
H
TCDT
Timer Data Register Lower
Timer Data Register Upper
Timer Control Status Register Lower
Timer Control Status Register Upper
Compare Clear Register Lower
Compare Clear Register Upper
16-bit Free-Run
Timer
0 0 0 0 0 0 0 0
B
0 0 0 0 0 0 0 0
B
0 0 0 0 0 0 0 0
B
0 - - 0 0 0 0 0
B
XXXXXXXX
B
XXXXXXXX
B
TCCS
CPCLR
Prohibited
00009B
H
DCSR
DMA Descriptor Channel
Specification Register
DMA Status Register Lower
DMA Status Register Upper
Program Address Detection Control
Status Register
Delay Interruption Factor Generation/
Release Register
R/W
μ
DMAC
0 0 0 0 0 0 0 0
B
00009C
H
00009D
H
DSRL
DSRH
R/W
R/W
0 0 0 0 0 0 0 0
B
0 0 0 0 0 0 0 0
B
00009E
H
PACSR
R/W
Address Match
Detection
0 0 0 0 0 0 0 0
B
00009F
H
DIRR
R/W
Delay Interrupt
- - - - - - - 0
B
0000A0
H
LPMCR
Low Power Consumption Mode
Register
R/W
Low Power
Consumption
Control Circuit
Clock
0 0 0 1 1 0 0 0
B
0000A1
H
0000A2
H
0000A3
H
0000A4
H
CKSCR
Clock Selection Register
R/W
1 1 1 1 1 1 0 0
B
Prohibited
DSSR
DMA Stop Status Register
Automatic Ready Function Selection
Register
External Address Output Control
Register
Bus Control Signal Control Register
Watchdog Control Register
Time-base Timer Control Register
Watch Timer Control Register
R/W
μ
DMAC
0 0 0 0 0 0 0 0
B
0000A5
H
ARSR
W
External Pin
0 0 1 1- - 0 0
B
0000A6
H
HACR
W
B
0000A7
H
0000A8
H
0000A9
H
0000AA
H
0000AB
H
0000AC
H
0000AD
H
EPCR
WDTC
TBTC
WTC
W
1 0 0 0
1 0 -
B
X - XXX 1 1 1
B
1 - - 0 0 1 0 0
B
1 0 0 0 1 0 0 0
B
R/W
R/W
R/W
Watchdog Timer
Time-base Timer
Watch Timer
Prohibited
DERL
DERH
DMA Enable Register Lower
DMA Enable Register Upper
Flash Memory Control Status
Register
R/W
R/W
μ
DMAC
0 0 0 0 0 0 0 0
B
0 0 0 0 0 0 0 0
B
0000AE
H
FMCR
R/W
Flash Memory
I/F
0 0 0 X 0 0 0 0
B
0000AF
H
Prohibited