MB90F243H
14
s HANDLING DEVICES
1. Preventing Latchup
Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to the input or output
pins other than medium-and high-voltage pins or if higher than the voltage which shown on “s Absolute Maximum
Ratings” is applied between VCC and VSS.
When latchup occurs, power supply current increases rapidly might thermally damage elements. When using,
take great care not to exceed the absolute maximum ratings.
In addition, for the same reasons take care to prevent the analog power supply from exceeding the digital power
supply.
2. Treatment of Unused Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down
resistors.
3. Precautions when Using an External Clock
When an external clock is used, drive X0 only.
4. Power Supply Pins
When there are several VCC and VSS pins, those pins that should have the same electric potential are connected
within the device when the device is designed in order to prevent misoperation, such as latch-up. However, all
of those pins must be connected to the power supply and ground externally in order to reduce unnecessary
emissions, prevent misoperation of strobe signals due to an increase in the ground level, and to observe the
total output current standards.
In addition, give a due consideration to the connection in that current supply be connected to VCC and VSS with
the lowest possible impedance.
Finally, it is recommended to connect a capacitor of about 0.1
F between VCC and VSS near this device as a
bypass capacitor.
X0
X1
For example an external clock