參數(shù)資料
型號(hào)： MB90673
廠商： Fujitsu Limited
英文描述： 16-Bit Proprietary Microcontroller(16位專(zhuān)用微控制器)
中文描述： 16位微控制器專(zhuān)利（16位專(zhuān)用微控制器）
文件頁(yè)數(shù)： 57/111頁(yè)
文件大小： 736K
代理商： MB90673
57
MB90670/675 Series
9. ICU (Input Capture)
ICU detects the rising edge, falling edge, or both edges of an externally input waveform and then saves the
counter value of the 24-bit free-run timer, while simultaneously generating an interrupt request for the CPU. The
module hardware consists of four 24-bit ICU data registers and an ICU control register. There are four external
input pins (AS0 to AS3), and each pin is used to implement the operation indicated below.
The capture precision of this ICU is equal to the operation cycle of the 24-bit free-run timer; if the 24-bit free-
run timer operates at 4 MHz, the capture precision is 250 ns.
AS0 to AS3: These input pins each have one ICU register; the counter value of the 24-bit free-run timer
can be retained when the specified valid edge (
↑
,
↓
, or
↑
↓
) is generated.
(1) Register Configuration
ICU control register upper
←
Bit no.
Read/write
→
Initial value
→
(R/W)
(0)
7
(R/W)
(0)
6
(R/W)
(0)
5
(R/W)
(0)
4
(R/W)
(0)
3
(R/W)
(0)
2
(R/W)
(0)
1
(R/W)
(0)
0
15
14
13
12
11
10
9
8
Address : 000053
H
IR2
IR3
IR1
IR0
IRE2
IRE3
IRE1
IRE0
ICC
ICR0L
ICR1L
ICR2L
ICR3L
ICR0L
ICR1L
ICR2L
ICR3L
ICR0H
ICR1H
ICR2H
ICR3H
ICR0H
ICR1H
ICR2H
ICR3H
ICC
Read/write
→
Initial value
→
(R/W)
(0)
(R/W)
(0)
15
(R/W)
(0)
14
(R/W)
(0)
13
(R/W)
(0)
12
(R/W)
(0)
11
(R/W)
(0)
10
(R/W)
(0)
9
ICU control register lower
Address : 000052
H
←
Bit no.
EG1A
EG1B
EG0B EG0A
EG3A
EG3B
EG2B EG2A
ICU lower data register upper
Address : channel 0 000061
H
channel 1 000065
H
channel 2 000069
H
channel 3 00006D
←
Bit no.
8
Read/write
→
Initial value
→
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
ICU upper data register upper
Address : channel 0 000063
H
channel 1 000067
H
channel 2 00006B
H
channel 3 00006F
←
Bit no.
15
14
13
12
11
10
9
8
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
Read/write
→
Initial value
→
7
6
5
4
3
2
1
0
Read/write
→
Initial value
→
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
ICU lower data register lower
Address : channel 0 000060
H
channel 1 000064
H
channel 2 000068
H
channel 3 00006C
←
Bit no.
7
6
5
4
3
2
1
0
Read/write
→
Initial value
→
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
ICU upper data register upper
Address : channel 0 000062
H
channel 1 000066
H
channel 2 00006A
H
channel 3 00006E
←
Bit no.
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