參數(shù)資料
型號: MB90672PFV
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: 16-bit Proprietary Microcontroller
中文描述: 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP80
封裝: PLASTIC, LQFP-80
文件頁數(shù): 46/124頁
文件大?。?/td> 2584K
代理商: MB90672PFV
MB90670/675 Series
46
3. Watchdog Timer
The watchdog timer is a 2-bit counter operating with an output of the timebase timer and resets the CPU when
the counter is not cleared for a preset period of time.
(1) Register Configuration
(2) Block Diagram
Watchdog timer control register (WDTC)
Address
0000A8
H
bit 15 . . . .. . . . . . ..
PONR STBR WRST ERST
SRST
WTE
WT1
WT0
(TBTC)
R : Read only
W: Write only
X : Indeterminate
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R
R
R
R
R
W
W
W
Initial value
XXXXX111
B
HCLK: Oscillation clock
PONR STBR WRST ERST SRST WTE
WT1
WT0
Watchdog timer control register (WDTC)
Start sleep mode
Start hold status
CLR and start
Watchdog timer
Overflow
To internal reset
generation circuit
Counter clear
control circuit
Count clock
selector
2-bit
counter
Watchdog reset
generation circuit
Clear
Divided-by-2
of HCLK
(Timebase timer counter)
×
2
1
×
2
2
. . .
×
2
8
×
2
9
×
2
10
×
2
11
×
2
12
×
2
13
×
2
14
×
2
15
×
2
16
×
2
17
×
2
18
CLR
2
4
CLR
Start stop mode
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