參數(shù)資料
型號： MB90623PFV
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 9-Bit Bus-Interface D-type Latches With 3-State Outputs 24-CDIP -55 to 125
中文描述： 16-BIT, MROM, 24 MHz, MICROCONTROLLER, PQFP100
封裝： PLASTIC, LQFP-100
文件頁數(shù)： 73/80頁
文件大?。?/td> 1304K
代理商： MB90623PFV
73
MB90620A Series
Table 18 Branch 1 Instructions [31 Instructions]
*1: 4 when branching, 3 when not branching.
*2: (b) + 3
×
(c)
*3: Read (word) branch address.
*4: W: Save (word) to stack; R: read (word) branch address.
*5: Save (word) to stack.
*6: W: Save (long word) to W stack; R: read (long word) R branch address.
*7: Save (long word) to stack.
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
Mnemonic
#
~
RG
B
Operation
L
H
A
H
I
S
T
N
Z
V
C
RM
W
BZ/BEQ
BNZ/BNE
BC/BLO
BNC/BHS
BN
BP
BV
BNV
BT
BNT
BLT
BGE
BLE
BGT
BLS
BHI
BRA
rel
rel
rel
rel
rel
rel
rel
rel
rel
rel
rel
rel
rel
rel
rel
rel
rel
JMP
JMP
JMP
JMP
JMPP
JMPP
JMPP
@A
addr16
@ear
@eam
@ear *
3
@eam *
3
addr24
CALL
CALL
CALL
CALLV
CALLP
@ear *
4
@eam *
4
addr16 *
5
#vct4 *
5
@ear *
6
CALLP
@eam *
6
CALLP
addr24 *
7
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
3
2
2+
2
2+
4
2
2+
3
1
2
2+
4
*
1
*
1
*
1
*
1
*
1
*
1
*
1
*
1
*
1
*
1
*
1
*
1
*
1
*
1
*
1
*
1
*
1
2
3
3
4+ (a)
5
6+ (a)
4
6
7+ (a)
6
7
10
11+ (a)
10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
2
0
0
1
0
0
0
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
(c)
0
(d)
0
(c)
2
×
(c)
(c)
2
×
(c)
2
×
(c)
*
2
2
×
(c)
Branch when (Z) = 1
Branch when (Z) = 0
Branch when (C) = 1
Branch when (C) = 0
Branch when (N) = 1
Branch when (N) = 0
Branch when (V) = 1
Branch when (V) = 0
Branch when (T) = 1
Branch when (T) = 0
Branch when (V) xor (N) = 1
Branch when (V) xor (N) = 0
Branch when ((V) xor (N)) or (Z) = 1
Branch when ((V) xor (N)) or (Z) = 0
Branch when (C) or (Z) = 1
Branch when (C) or (Z) = 0
Branch unconditionally
word (PC)
←
(A)
word (PC)
←
addr16
word (PC)
←
(ear)
word (PC)
←
(eam)
word (PC)
←
(ear), (PCB)
←
(ear +2)
word (PC)
←
(eam), (PCB)
←
(eam +2)
word (PC)
←
ad24 0 to 15,
(PCB)
←
ad24 16 to 23
word (PC)
←
(ear)
word (PC)
←
(eam)
word (PC)
←
addr16
Vector call instruction
word (PC)
←
(ear) 0 to 15
(PCB)
←
(ear) 16 to 23
word (PC)
←
(eam) 0 to 15
(PCB)
←
(eam) 16 to 23
word (PC)
←
addr0 to 15,
(PCB)
←
addr16 to 23
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相關(guān)PDF資料
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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