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參數(shù)資料
| 型號： | MB90622PFV |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 9-Bit Bus-Interface D-type Latches With 3-State Outputs 28-LCCC -55 to 125 |
| 中文描述： | 16-BIT, MROM, 24 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 41/80頁 |
| 文件大?。?/td> | 1304K |
| 代理商： | MB90622PFV |
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41
MB90620A Series
9. DTP/External Interrupt
The DTP (Data Transfer Peripheral) is a peripheral, positioned between peripherals external to the device and
the F
2
MC-16L CPU, that accepts DMA requests or interrupt requests generated by external peripherals and
transfers them to the F
2
MC-16L CPU to activate the Intelligent I/O Service or interrupt processing.
In the case of the Intelligent I/O Service, there are two request levels that can be selected: high and low; in the
case of an external interrupt request, there are a total of four request levels that can be selected: high, low, rising
edge and falling edge.
(1) Register Configuration
(2) Block Diagram
10. Watchdog Timer, Timebase Timer, and Watch Timer Functions
The watchdog timer consists of a 2-bit watchdog counter that uses the carry signal from the 18-bit timebase
timer or the 15-bit watch timer as a clock source, a control register, and a watchdog reset controller.
The timebase timer consists of an 18-bit timer and a circuit that controls interval interrupts. Note that the timebase
timer uses the main clock, regardless of the setting of the MCS bit and SCS bit in CKSCR.
The watch timer consists of a 15-bit timer and a circuit that controls interval interrupts. Note that the watch timer
uses the sub clock, regardless of the setting of the MCS bit and SCS bit in CKSCR.
(1) Register Configuration
Address:
:
EIRR
ENIR
15
0
000029
H
000028
H
bit
DTP/Interrupt enable register
Address:
:
ELVR
15
0
00002B
H
00002A
H
bit
Request level setting register
4
4
4
8
3
DTP/Interrupt enable register
DTP/Interrupt source register
Request level setting register
Gate
Source F/F
Edge detector
Request input
F
2
M
Address: 0000A8
H
PONR
—
ERST
SRST
WT1
WT0
Watchdog timer control register
(WDTC)
Timebase timer control register
(TBTC)
7
6
5
4
3
2
1
0
Address: 0000A9
H
bit
Address:
15
14
13
12
11
10
9
8
0000AA
H
bit
Watch timer control register
(WTC)
7
6
5
4
3
2
1
0
bit
WRST
WTE
WDCS
SCE
WTOF
WTR
WTC1
WTC0
WTIE
WTC2
Reserved
—
TBIE
TBOF
TBC1
TBC0
—
TBR
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MB90P623A | 16-bit Proprietary Microcontroller |
| MB90P623PFV | 16-bit Proprietary Microcontroller |
| MB90623PFV | 9-Bit Bus-Interface D-type Latches With 3-State Outputs 24-CDIP -55 to 125 |
| MB90632APF | 9-Bit Bus-Interface D-type Latches With 3-State Outputs 24-CDIP -55 to 125 |
| MB90P634A | 16-bit Proprietary Microcontroller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB90623A | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16-bit Proprietary Microcontroller |
| MB90623PFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16-bit Proprietary Microcontroller |
| MB90632A | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16-bit Proprietary Microcontroller |
| MB90632APF | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16-bit Proprietary Microcontroller |
| MB90632APFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16-bit Proprietary Microcontroller |
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