參數(shù)資料
型號： MB90622A
廠商： Fujitsu Limited
英文描述： 16-Bit Proprietary Microcontroller(16位專用微控制器)
中文描述： 16位微控制器專利（16位專用微控制器）
文件頁數(shù)： 44/82頁
文件大小： 797K
代理商： MB90622A
MB90620A Series
44
12.Low-power Consumption Controller (CPU Intermittent Operation Function, Oscillation
Stabilization Delay Time, Clock Multiplier Function)
The following are the operating modes: PLL sleep mode, PLL watch mode, Pseudo-watch mode, main clock
mode, main sleep mode, main watch mode, main stop mode, sub clock mode, sub sleep mode, sub watch
mode, sub stop mode, and hardware standby mode. Aside from the PLL clock mode, all of the other operating
modes are low-power consumption modes.
In main clock mode and main sleep mode, the main clock (main OSC oscillation clock) and the sub clock (sub
OSC oscillation clock) operate. In these modes, the main clock divided by 2 is used as the operation clock, the
sub clock (sub OSC oscillation clock) is used as the timer clock, and the PLL clock (VCO oscillation clock) is
stopped.
In sub clock mode and sub sleep mode, only the sub clock operates. In these modes, the sub clock is used as
the operation clock, and the main clock and PLL clock are stopped.
In PLL sleep mode and main sleep mode, only the CPU’s operation clock is stopped; all clocks other than the
CPU clock operate.
In Pseudo-watch mode, only the watch timer and timebase timer operate.
In PLL watch mode, main watch mode, and sub watch mode, only the watch timer operates.
In this mode, only the sub clock is used for operation, while the main clock and the PLL clock are stopped (the
difference between the PLL timer mode, the main timer mode and the sub timer mode is that it resumes operation
after an interrupt in the PLL clock mode, the main clock modes and the sub clock mode respectively, and there
is no difference in the timer mode).
The main stop mode, sub stop mode, and hardware standby mode stop oscillation, making it possible to retain
data while consuming the least amount of power (The difference between the main stop mode and the sub stop
mode is that it resumes operation in the main clock mode and the sub clock mode respectively, and there is no
difference in the timer mode).
The CPU intermittent operation function intermittently runs the clock supplied to the CPU when accessing
registers, on-chip memory, on-chip resources, and the external bus. Processing is possible with lower power
consumption by reducing the execution speed of the CPU while supplying a hig-speed clock and using on-chip
resources.
The PLL clock multiplier can be selected as either 2, 4, 6, or 8 by setting the CS1 and CS0 bits. These clocks
are divided by 2 to be used as a machine clock.
The WS1 and WS0 bits can be used to set the main clock oscillation stabilization delay timer for when stop mode
and hardware standby mode are woken up.
(1) Register Configuration
Address: 0000A0
H
STP
SLP
RST
TMD
CG0
SSR
Low-power consumption
mode control register
(LPMCR)
Clock selection register
(CKSCR)
7
6
5
4
3
2
1
0
Address: 0000A1
H
bit
15
14
13
12
11
10
9
8
bit
SPL
CG1
SCM
MCM
WS0
SCS
CS1
CS0
WS1
MCS
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MB90632A 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16-bit Proprietary Microcontroller
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