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參數(shù)資料
| 型號： | MB90594G |
| 廠商： | Fujitsu Limited |
| 英文描述： | Quadruple 2-Input Positive-OR Gate 20-LCCC -55 to 125 |
| 中文描述： | 16位微控制器專有 |
| 文件頁數(shù)： | 35/51頁 |
| 文件大?。?/td> | 714K |
| 代理商： | MB90594G |
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MB90590/590G Series
35
*1:The interrupt request flag is cleared by the I
2
OS interrupt clear signal.
*2:The interrupt request flag is cleared by the I
2
OS interrupt clear signal. A stop request is available.
N/A:The interrupt request flag is not cleared by the I
2
OS interrupt clear signal.
Note:
For a peripheral module with two interrupt for a single interrupt number, both interrupt request flags are
cleared by the I
2
OS interrupt clear signal.
At the end of I
2
OS, the I
2
OS clear signal will be asserted for all the interrupt flags assigned to the same in-
terrupt number. If one interrupt flag starts the I
2
OS and in the meantime another interrupt flag is set by a
hardware event, the later event is lost because the flag is cleared by the I
2
OS clear signal caused by the
first event. So it is recommended not to use the I
2
OS for this interrupt number.
If I
2
OS is enabled, I
2
OS is initiated when one of the two interrupt signals in the same interrupt control register
(ICR) is asserted. This means that different interrupt sources share the same I
2
OS Descriptor which should
be unique for each interrupt source. For this reason, when one interrupt source uses the I
2
OS, the other
interrupt should be disabled.
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