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| 型號： | MB90428GPFV |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-Bit Original Microcontroller |
| 中文描述： | 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 87/99頁 |
| 文件大?。?/td> | 1706K |
| 代理商： | MB90428GPFV |
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MB90420G/5G (A) Series
87
Table 13 Signed Multiplication and Division Instructions (Byte/Word/Long Word) [11 Instructions]
*1: Set to 3 when the division-by-0, 8 or 18 for an overflow, and 18 for normal operation.
*2: Set to 3 when the division-by-0, 10 or 21 for an overflow, and 22 for normal operation.
*3: Set to 4 + (a) when the division-by-0, 11 + (a) or 22 + (a) for an overflow, and 23 + (a) for normal operation.
*4: Positive dividend: Set to 4 when the division-by-0, 10 or 29 for an overflow, and 30 for normal operation.
Negative dividend: Set to 4 when the division-by-0, 11 or 30 for an overflow and 31 for normal operation.
*5: Positive dividend:Set to 4 + (a) when the division-by-0, 11 + (a) or 30 + (a) for an overflow, and 31 + (a) for
normal operation.
Negative dividend:Set to 4 + (a) when the division-by-0, 12 + (a) or 31 + (a) for an overflow, and 32 + (a) for
normal operation.
*6: When the division-by-0, (b) for an overflow, and 2
×
(b) for normal operation.
*7: When the division-by-0, (c) for an overflow, and 2
×
(c) for normal operation.
*8: Set to 3 when byte (AH) is zero, 12 when the result is positive, and 13 when the result is negative.
*9: Set to 3 when byte (ear) is zero, 12 when the result is positive, and 13 when the result is negative.
*10: Set to 4 + (a) when byte (eam) is zero, 13 + (a) when the result is positive, and 14 + (a) when the result is negative.
*11: Set to 3 when word (AH) is zero, 12 when the result is positive, and 13 when the result is negative.
*12: Set to 3 when word (ear) is zero, 16 when the result is positive, and 19 when the result is negative.
*13: Set to 4 + (a) when word (eam) is zero, 17 + (a) when the result is positive, and 20 + (a) when the result is
negative.
Notes: When overflow occurs during DIV or DIVW instruction execution, the number of execution cycles takes
two values because of detection before and after an operation.
When overflow occurs during DIV or DIVW instruction execution, the contents of AL are destroyed.
For (a) to (d), refer to “Table 4 Number of Execution Cycles for Effective Address in Addressing Modes”
and “Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles.”
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
DIV
A
DIV
A, ear
DIV
A, eam
DIVW
A, ear
DIVW
A, eam
MULU
MULU
MULU
MULUW A
MULUW A, ear
MULUW A, eam
A
A, ear
A, eam
2
2
2 +
2
2+
2
2
2 +
2
2
2 +
*1
*2
*3
*4
*5
*8
*9
*10
*11
*12
*13
0
1
0
1
0
0
1
0
0
1
0
0
0
*6
0
*7
0
0
(b)
0
0
(c)
word (AH) /byte (AL)
Quotient
→
byte (AL)
Remainder
→
byte (AH)
word (A)/byte (ear)
Quotient
→
byte (A)
Remainder
→
byte (ear)
word (A)/byte (eam)
Quotient
→
byte (A)
Remainder
→
byte (eam)
long (A)/word (ear)
Quotient
→
word (A)
Remainder
→
word (ear)
long (A)/word (eam)
Quotient
→
word (A)
Remainder
→
word (eam)
byte (AH) *byte (AL)
→
word (A)
byte (A) *byte (ear)
→
word (A)
byte (A) *byte (eam)
→
word (A)
word (AH) *word (AL)
→
long (A)
word (A) *word (ear)
→
long (A)
word (A) *word (eam)
→
long (A)
Z
Z
Z
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–
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–
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