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參數(shù)資料
| 型號(hào)： | MB90099 |
| 廠商： | Fujitsu Limited |
| 英文描述： | On-Screen Display Controller |
| 中文描述： | 屏幕顯示控制器 |
| 文件頁數(shù)： | 26/36頁 |
| 文件大小： | 1071K |
| 代理商： | MB90099 |
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MB90099
26
3.
Notes on Issuing Commands
(1) Initialization
When a reset signal is input (“L” level signal input to the RESET pin) , the MB90099 enters display-off state(*).
The contents of VRAM (the character RAM and the line RAM) are undefined.
Immediately after release of the input signal to the MB90099, issue the following commands to initialize control
operation.
Dot clock control 1 (command 11-2)
I/O pin control (command 13-0)
This must be done before setting all command data and all RAM contents. (VRAM settings require normal dot
clock input and normal sync signal input.)
* : The reset input initializes control bits as follows.
Screen output control 1A (command 5-00)
SDS
=
0 Sprite Off
UDS
=
0 Screen background Off
DSP
=
0 Character, character background, line background Off
I/O pin control (command 13-0)
DCX
=
0 VC0, VC1, VC2, VC3 pins set to positive logic output
DBX
=
0 BLKA, BLKB, BLKC pins set to positive logic output
(2) Command refresh
Command data to the MB90099 and the contents of internal VRAM are stored as long as power is supplied to
the MB90099. However, there may be cases in which the serial control, sync, or dot clock signals become
abnormal due to causes such as external noise, preventing the internal registers and VRAM from being set
properly. It is therefore recommended that all command data and VRAM data be refreshed periodically to ensure
that this data is correct.
(3) Command issue timing
When any control command, including a VRAM write command such as a character data setting or line control
data setting command is issued, the command is executed immediately and the result is reflected on the screen.
When such a command is issued during a display period, the display in the relevant field may experience
momentary distortion. To avoid this, it is recommended that commands be issued during the vertical blanking
interval. However that with a command 5-00 (screen output control 1A) in which one or more of the DSP, SDS,
or UDS control bits is switched from OFF to ON, the display will wait until the next vertical sync signal after the
command is issued and the display will start from the top of the scanning field.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB90099PFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:On-Screen Display Controller |
| MB900F-R | 制造商:IBase Technology (USA) Inc. 功能描述:MATX, LGA775, DUALCORE, 945G+ICH7, W/ ICH LANX1 + 88E8052 GB - Bulk |
| MB900-R | 制造商:IBase Technology (USA) Inc. 功能描述:MATX, LGA775, DUALCORE, 945G+ICH7, W/ ICH LANX1, VGA, COMX4, - Bulk |
| MB90214 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16-bit Proprietary Microcontroller |
| MB90214PF | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16-bit Proprietary Microcontroller |
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