參數(shù)資料
型號: MB90099
廠商: Fujitsu Limited
英文描述: On-Screen Display Controller
中文描述: 屏幕顯示控制器
文件頁數(shù): 12/36頁
文件大?。?/td> 1071K
代理商: MB90099
MB90099
12
(2) Vertical and horizontal sync signal input timing
(V
DD
=
2.4 V to 3.6 V, V
GND
=
0 V, Ta
=
20
°
C to
+
70
°
C)
*1 : During the horizontal sync signal pulse period, the MB90099 stops its internal operation, disabling writing to the
internal VRAM. Therefore, the horizontal sync signal pulse width and VRAM write cycle (command 2 or command
4 issuance cycle) should be set so that the horizontal sync signal pulse width is shorter than the VRAM write cycle.
*2 : In the vertical sync signal detection cycle, do not change the vertical sync signal (detection edge) when it is
close to the horizontal sync signal edge. This may result in distortion of the display due to fluctuations in the
sync signal.
*3 : VVE, VHE and HE are control bits of Command 13-0 (I/O pin control) .
(Continued)
Parameter
Symbol
Pin name
Value
Unit
Min.
18
Max.
Horizontal sync signal rise time
t
HR
HSYNC
200
ns
Horizontal sync signal fall time
t
HF
200
ns
Vertical sync signal rise time
t
VR
VSYNC
200
ns
Vertical sync signal fall time
t
VF
200
6
ns
Horizontal sync signal pulse width *
1
t
WH
HSYNC
Dot clock
μ
s
Vertical sync signal setup time1 *
2
(Except for VVE
=
1, VHE
=
1, HE
=
1) *
3
Vertical sync signal setup time2 *
2
(VVE
=
1, VHE
=
1, HE
=
1) *
3
Vertical sync signal detection hold time
t
VS
VSYNC
4
1H
4
Dot clock
t
VS
VSYNC
6
1H
14
Dot clock
t
VH
VSYNC
2
20
H
Vertical sync signal pulse width
t
WV
VSYNC
2
H
VSYNC : Leading-edge operation (VVE
=
0)
HSYNC : VSYNC detection at the trailing edge (VHE
=
1)
0.8 V
DD
0.2 V
DD
0.8 V
DD
0.2 V
DD
VSYNC
t
VS
t
WH
t
VH
t
HF
t
HR
t
VR
0.8 V
DD
0.2 V
DD
0.8 V
DD
0.2 V
DD
HSYNC
t
VF
t
WV
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