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參數(shù)資料
| 型號： | MB89PV950CF |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 5 MHz, MICROCONTROLLER, CQFP64 |
| 封裝： | 0.80 MM PITCH, PIGGY BACK, MQFP-64 |
| 文件頁數(shù)： | 86/110頁 |
| 文件大小： | 619K |
| 代理商： | MB89PV950CF |
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HARDWARE CONFIGURATION
2– 62
(4) RAM for display
The LCD controller/driver contains the 21
× 8-bit RAM for generating a
segment output signal. The data of this RAM is automatically read in
synchronization with the common signal select timing and the waveform
corresponding to this data is output from the segment output pin.
42 segment signals correspond to 21 locations of the display RAM. Each
location bit is in synchronization with the common signal select timing: bits
0 and 4 with COM0, bits 1 and 5 with COM1, bits 2 and 6 with COM2, and
bits 3 and 7 with COM3. If the value of each bit is 1, the signal is converted
to LCD voltage and if it is 0, the signal is converted to non-LCD and is
output. However, at reset, COM0 to COM3 and SEG0 to SEG19 go Low,
and SEG20 to SEG41 go high impedance because they also serve as I/O
ports.
The waveform is output from the segment pins irrespective of the CPU
operation. Therefore, reading and writing from and to the display RAM are
possible in any timing.
When using SEG20 to SEG41 as general-purpose output ports, the 11
upper bytes (006E
H to 0078H) are usually used as RAM.
Address
COM3COM2COM1COM0
Segment
064H
b3
b2
b1
b0
SEG00
b7
b6
b5
b4
SEG01
065H
b3
b2
b1
b0
SEG02
b7
b6
b5
b4
SEG03
:
06DH
b3
b2
b1
b0
SEG18
b7
b6
b5
b4
SEG19
06EH
b3
b2
b1
b0
SEG20
b7
b6
b5
b4
SEG21
06FH
b3
b2
b1
b0
SEG22
b7
b6
b5
b4
SEG23
070H
b3
b2
b1
b0
SEG24
b7
b6
b5
b4
SEG25
071H
b3
b2
b1
b0
SEG26
b7
b6
b5
b4
SEG27
072H
b3
b2
b1
b0
SEG28
b7
b6
b5
b4
SEG29
073H
b3
b2
b1
b0
SEG30
b7
b6
b5
b4
SEG31
074H
b3
b2
b1
b0
SEG32
b7
b6
b5
b4
SEG33
075H
b3
b2
b1
b0
SEG34
b7
b6
b5
b4
SEG35
076H
b3
b2
b1
b0
SEG36
b7
b6
b5
b4
SEG37
077H
b3
b2
b1
b0
SEG38
b7
b6
b5
b4
SEG39
078H
b3
b2
b1
b0
SEG40
b7
b6
b5
b4
SEG41
Peripherals
Multiplexed
with port 0
Multiplexed
with port 1
Multiplexed
with port 2
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