參數(shù)資料
型號: MB89PV950CF
元件分類: 微控制器/微處理器
英文描述: 8-BIT, 5 MHz, MICROCONTROLLER, CQFP64
封裝: 0.80 MM PITCH, PIGGY BACK, MQFP-64
文件頁數(shù): 69/110頁
文件大?。?/td> 619K
代理商: MB89PV950CF
HARDWARE CONFIGURATION
2– 46
(4) Description of operation
(a) Operation modes
The UART has the operation modes listed in Table 2–6; they can be switched
by setting the value at the serial mode control register 1 (SMC1).
However, the stop bit length can be specified only for the transmitter
channel. The 1-bit length is always specified for the receiver channel.
(b) Interrupt occurrence and flag setting conditions
The UART has three flags and two interrupt sources.
The three flags are ORFE, RDRF, and TDRE. The ORFE flag is an overrun/
framing error flag which is set when an error occurs at receiving. The RDRF
flag indicates that the receive data is ready at the SIDR register. The TDRE
flag indicates that writing to the transmit data register (SODR) is enabled.
The two interrupt sources are one for receiving, and one for transmitting.
At receiving, an interrupt is requested by the RDRF or ORFE flag. At
transmitting, an interrupt is requested by the TDRE flag.
a. Receiving in modes 0, 1, and 3
Both the RDRF (receive data register full) and ORFE (overrun/framing
error) flags are set when receiving and transfer are completed and the
last stop bit is detected. An interrupt request is then output to the CPU.
When the RDRF flag is active, the received data is transferred to the
serial data input register (SIDR).
Fig. 2.15 RDRF Flag Set Timing
Table 2–6 Operation Modes of UART
Mode
Parity
Data Length
Clock Mode
Stop Bit Length
0
Provided
4
Asynchronous/synchronous
1 bit or 2 bits
Not provided
5
Asynchronous/synchronous
1 bit or 2 bits
1
Provided
7
Asynchronous/synchronous
1 bit or 2 bits
Not provided
8
Asynchronous/synchronous
1 bit or 2 bits
3
Provided
8
Asynchronous/synchronous
1 bit or 2 bits
Not provided
9
Asynchronous/synchronous
1 bit or 2 bits
Peripherals
Data
SIN interrupt
RDRF
Stop
(Stop)
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