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參數(shù)資料
| 型號(hào)： | MB89P637-SH |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 10 MHz, MICROCONTROLLER, PDIP64 |
| 封裝： | SHRINK, DIP-64 |
| 文件頁數(shù)： | 110/153頁 |
| 文件大?。?/td> | 7326K |
| 代理商： | MB89P637-SH |
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Figures
Fig. 1.1
Block Diagram (MB89635)........................................................................................................ 1-5
Fig. 1.2
Pin Assignment (DIP-64P-M01 and MDP-64C-P02) ................................................................ 1-6
Fig. 1.3
Pin Assignment (FPT-64P-M09) ............................................................................................... 1-6
Fig. 1.4
Pin Assignment (MQP-64C-P01 and FPT-64P-M06)................................................................ 1-7
Fig. 1.5
Package dimension .................................................................................................................. 1-8
Fig. 1.6
Package dimension (QFP)........................................................................................................ 1-9
Fig. 1.7
Package dimension (MB89PV630) ......................................................................................... 1-10
Fig. 2.1
Memory Space of MB89630 Series of Microcontrollers ........................................................... 2-3
Fig. 2.2
Arrangement of 16-bit Data in Memory ....................................................................................2-5
Fig. 2.3
Arrangement of 16-bit Data during Execution of Instruction ..................................................... 2-5
Fig. 2.4
Structure of Program Status ..................................................................................................... 2-6
Fig. 2.5
Rule for Translating Real Addresses at General-purpose Register Area ................................. 2-7
Fig. 2.6
Register Bank Configuration..................................................................................................... 2-8
Fig. 2.7
Memory Maps in Various Modes .............................................................................................. 2-9
Fig. 2.8
Interrupt-processing Flowchart ............................................................................................... 2-26
Fig. 2.9
Ports 0 and 1 (in Single-chip Mode) ....................................................................................... 2-29
Fig. 2.10 Port 2 (in Single-chip Mode) ................................................................................................... 2-30
Fig. 2.11 Port 3 ...................................................................................................................................... 2-32
Fig. 2.12 Port 4 ...................................................................................................................................... 2-34
Fig. 2.13 Port 5 ...................................................................................................................................... 2-35
Fig. 2.14 Port 6 ...................................................................................................................................... 2-36
Fig. 2.15 Port 7 ...................................................................................................................................... 2-37
Fig. 2.16 Timer Operation...................................................................................................................... 2-44
Fig. 2.17 PWM Pulse Output ................................................................................................................. 2-45
Fig. 2.18 PWM Wave Output at CH1-2 PWM Mode .............................................................................. 2-46
Fig. 2.9
RDRF Flag Set Timing ........................................................................................................... 2-67
Fig. 2.10 ORFE Flag Set Timing ........................................................................................................... 2-68
Fig. 2.11 TDRE Flag Set Timing (Mode 0) ............................................................................................ 2-69
Fig. 2.12 Shift Start/Stop Timing ........................................................................................................... 2-77
Fig. 2.13 Input/Output Shift Timing ........................................................................................................ 2-78
Fig. 2.14 Block Diagram of Watchdog Timer ......................................................................................... 2-95
Fig. 3.15 Clock Pulse Generator.............................................................................................................. 3-3
Fig. 3.16 Outline of Reset Operation ....................................................................................................... 3-4
Fig. 3.17 Interrupt-processing Flowchart ................................................................................................. 3-6
Fig. 3.18 Memory Map in Various Modes ................................................................................................ 3-8
Fig. 3.19 External-access Timing Chart .................................................................................................. 3-8
Fig. 3.20 External Peripheral/Memory Connection ..................................................................................3-9
Fig. 3.21 Ready Input Timing Chart (Write Cycle).................................................................................3-10
Fig. 3.22 Ready Generation Circuit ....................................................................................................... 3-10
Fig. 3.23 Hold Timing ............................................................................................................................ 3-11
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