參數(shù)資料
型號: MB89P637-SH
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 10 MHz, MICROCONTROLLER, PDIP64
封裝: SHRINK, DIP-64
文件頁數(shù): 108/153頁
文件大小: 7326K
代理商: MB89P637-SH
HARDWARE CONFIGURATION
2-35
P50 to P53 N-ch open-drain-type I/O ports (also used as resource input/output)
Switching input and output
These ports have no register for specifying input or output. When using as an input port, set 1 at the
Port Data Register (PDR).
Operation for output port
The value written at the PDR is output to the pin. When the PDR is read, usually, the value of the pin is
read instead of the contents of the output latch. However, when the Read Modify Write instruction is
executed, the contents of the output latch are read. Therefore, the bit-processing instruction can be
used even if input and output are mixed with each other.
Operation for input port
When using as the input port, set 1 at the PDR to turn off the output transistor. When the PDR is read
under this condition, the value of the pin can always be read.
Operation for resource output
When using as a resource output, setting is performed by the resource output- enable bit (see descrip-
tion of each resource). Even if output of each resource is enabled, the port can be read other than when
the Read Modify Write instruction is read. Therefore, the state of the pin can be checked.
Operation for resource input
The value of the pin is always input to the port serving also as the resource input irrespective of the set-
ting of the resource. When using an external signal at the resource, set 1 at the PDR.
State when reset
The PDR is initialized to 1 at reset, so the output transistor is turned off at all bits.
State in stop mode
When the SPL bit of the standby-control register is set to 1, in the stop mode, the output impedance
goes High irrespective of the value of the PDR. (Pins with activated pull-up resistors are in the pull-up
state.)
Fig. 2.13 Port 5
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