參數(shù)資料
型號(hào)： MB89P215PFV
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 12.5 MHz, MICROCONTROLLER, PDSO30
封裝： PLASTIC, SSOP-30
文件頁(yè)數(shù)： 15/50頁(yè)
文件大小： 875K
代理商： MB89P215PFV
MB89210 Series
22
The RP points to the address of the register bank currently in use. The relationship between the pointer contents
and the actual address is based on the conversion rule shown next.
The CCR consists of the bits indicating arithmetic operation results or transfer data contents and the bits that
control CPU operations at the time of an interrupt.
H flag
: Set to 1 if calculations result in carry operations from bit 3 to bit 4 or borrow operations from bit 4
to bit 3, otherwise set to 0.
The flag is for decimal adjustment instructions; do not use for other than additions and subtractions.
I flag
:
This flag is set to 1 if interrupts are enabled, and 0 if interrupts are prohibited. The default value at
reset is 0.
IL1, 0
: Indicates the level of the interrupt currently enabled.
An interrupt is processed only if its level is higher than the value this bit indicates.
IL1
IL0
Interrupt level
High-low
00
1
Higher
Lower = no interruption
01
10
2
11
3
N flag
: Set to 1 if the highest bit is 1 after a calculation, otherwise cleared to 0.
Z flag
: Set to 1 if a calculation result is 0, otherwise cleared to 0.
V flag
: Set to 1 if a 2’s complement overflow results during a calculation, otherwise cleared to 0.
C flag
: Set to 1 if a calculation results in a carry or borrow operation from bit 7, otherwise cleared to 0.
This is also the shift-out value in a shift instruction.
Rule for Conversion of Actual Addresses in the General-purpose Register Area
"0"
"1"
R4
R3
R2
R1
R0
b2
b1
b0
A7
A6
A5
A4
A3
A2
A1
A0
A15 A14 A13 A12 A11 A10
A9
A8
Generated address
RP higher bits
OP code lower bits
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