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CHAPTER 4 I/O Ports
MB89960 series
4.6 Port 4
4.6.2 Operation of Port 4
This section describes the operation of port 4.
s Operation of Port 4
q Operation as an output port
Writing data to the PDR4 register stores the data in the output latch. When the output
latch value is “0”, the output transistor turns “ON” and an “L” level is output from the
pin. When the output latch value is “1”, the transistor turns “OFF” and the pin goes to
high impedance. If a pull-up is provided for the output pin, the pin goes to the pull-up
state when the output latch is “1”.
Reading the PDR4 register returns the pin value (“0” or “1”, the same value as the
output latch).
Note: As the bit manipulation instructions (SETB and CLRB) read the output latch value rather
than the pin level, the instructions do not change the output latch values for bits other
than the bit being set or cleared.
q Operation as a resource output
Set the output enable bit of the resource to use a pin as a resource output. As the pin value can
be read even if the resource output is enabled, the resource output value can be read. The
PDR4 register value has no effect on the resource output enable.
q Operation as an analog input
Write “1” to the corresponding bit of the PDR4 register if using a pin as an analog input. This
turns the output transistor “OFF” and sets the pin to high impedance.
q Operation as a resource input
The pin value is continuously input for ports that share a pin with a resource input, regardless of the
PDR4 register setting and of whether or not the resource is using the input pin. When the resource is
using the external signal, set the PDR4 register bit to “1” to turn the output transistor “OFF”.
q Operation at reset
Resetting the CPU initializes the PDR4 register values to “1”. This turns “OFF” the output
transistor for all pins (all pins become input ports) and sets the pins to high impedance.
q Operation in stop mode
The output transistors are forcibly turned “OFF” and the pins go to high impedance if the pin
state specification bit in the standby control register (STBC: SPL) is “1” when the device
changes to stop mode.
Table 4.5.2 lists the port 4 pin states.
SPL: Pin state specification bit in the standby control register (STBC: SPL)
Hi-z: High impedance
Note: Pins with the pull-up resistor selected go to the “H” level rather than to high impedance
when the output transistor is “OFF”.
Table 4.6.2 Port 4 Pin States
Pin
Normal Mode, Sleep Mode,
Stop Mode (SPL=0)
Stop Mode (SPL=1)
Reset
P40/AN0 - P45/SCL
General-purpose I/O ports/
resource I/O
Hi-z