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| 型號(hào)： | MB89965PF-G-XXX |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PQFP48 |
| 封裝： | 12 X 12 MM, 0.80 MM PITCH, PLASTIC, QFP-48 |
| 文件頁(yè)數(shù)： | 149/278頁(yè) |
| 文件大?。?/td> | 1847K |
| 代理商： | MB89965PF-G-XXX |
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CHAPTER 12 I2C Interface
MB89960 series
12.1 I2C Interface
The I2C Interface is a two wires, bidirectional serial bus which provides a simple
efficient way for data exchange between devices. This two wire bus minimizes the
interconnection between the devices and eliminates the need of address decoder, so
that less PCB traces and economic hardware structure resulted.
It is fully compatible to I2C bus from Philips and has the features as master/slave
transmit/receive, arbitration loss detection, slave address/general call address
detection, generate/detect START or STOP condition and bus error detection.
s I2C Interface Function
The function of the I2C interface is to use two bidirectional serial bus lines SDA (serial data line)
and SCL (serial clock line) for data transfer. All devices connected on it must have open drain or
open collector output, logic “and” function is exercised in both lines with two pulling up resistors.
Each device connected to the bus is software addressable by a unique address and simple
master/slave relationships exist at all times; master can operate as master-transmitters or as
master-receivers.
The I2C bus system is a true multi-master bus including collision detection and arbitration to
prevent data corruption if two or more masters simultaneously initiate data transfer. The
maximum data rate is limited on 100 Kbit/s and the maximum number of ICs that can be
connected to the same bus is limited by a maximum bus capacitance of 400pF.
The I2C interface is fully compatible to I2C bus from Philips and the System Management Bus
from Intel Corp. and has the following features:
Master/slave transmit/receive.
Arbitration lost detection with automatically switching from master to slave.
Slave address and general call address comparison.
Detect the direction of data transfer.
Generate/detect START or STOP condition.
Repeated START condition generation/detection.
Bus error detection.
Software programmable for one of 32 different serial clock frequencies.
Software selectable acknowledge bit.
Generate/recognize the acknowledge bit.
Interrupt driven byte by byte data transfer.
Selectable input buffer for I2C interface and System Management Bus interface.
Noise cancelling capability of input spike up to 20n sec.
The MB89960 series has a single channel I2C interface circuit.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MB89965PFM-G-XXX | 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PQFP48 |
| MB89965PFV-G-XXX | 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PQFP64 |
| MB89P965PFV | 8-BIT, OTPROM, 10 MHz, MICROCONTROLLER, PQFP64 |
| MB89F202RAPFV-GE1 | 8-BIT, FLASH, 12.5 MHz, MICROCONTROLLER, PDSO34 |
| MB89F202YPFV | 8-BIT, FLASH, 12.5 MHz, MICROCONTROLLER, PDSO34 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB8996X | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit Proprietary Microcontroller |
| MB89983 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit Proprietary Microcontroller |
| MB89983-XXX-PFM | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit Proprietary Microcontroller |
| MB89983-XXX-PFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit Proprietary Microcontroller |
| MB8998X | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit Proprietary Microcontroller |
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