HARDWARE CONFIGURATION
2-83
(4) Description of operation
(a) A/D mode
(1) Start or restart by program
Writing 0 at the ADMD bit (bit 2) of the ADC2 gives the A/D mode. Writing 1 at the AD bit (bit 0) of the
ADC1 starts the A/D conversion. If 1 is written at the AD bit (bit 0) of ADC1 during A/D conversion,
the conversion operation is canceled and restarted.
(2) Start/restart by external clock
Writing 1 at EXT (bit 1) of ADC2 sets the AD mode to wait for starting by the external clock. A/D con-
ver sion is started after detecting the rising edge of the clock pulse selected by the ADCK bit (bit 4) of
ADC2. If the rising clock pulse occurs during the operation, the conversion operation is canceled and
restarted. When the external clock is used for starting or restarting by setting EXT (bit 1) to 1, A/D
conversion cannot be started or restarted by the program.
(3) End
When A/D conversion is terminated, the result of the operation is stored in the data register and AD1
(bit 3) of ADC1 is set. At that time, an interrupt request is output when ADIE (bit 2) of ADC2 is 1.
The conversion result is stored in the data register until next conversion starts. Therefore, read the
conversion result before starting the next conversion. The result stored in the register is lost when the
operation is restarted.
(4) Continuous start of AD conversion by external clock
The A/D conversion can be started continuously by providing an external clock based on the conver
sion time and operation result reading time.
(b) Sense Mode
(1) Comparison/recomparison by program
Preprogram a specified comparison value in the data register.
Writing 1 at ADMD (bit 2) of ADC2 gives the sense mode. Writing 1 at AD (bit 0) of ADC1 starts com-
pari son. If 1 is written at AD (bit 0) of ADC1 during comparison, the operation is canceled and
restarted.
(2) Comparison/recomparison by external clock
Preprogram a specified comparison value in the data register.
Writing 1 at EXT (bit 1) of ADC2 sets the sense mode to wait for starting by the external clock. Compari
son is started at after detecting rising edge of the clock pulse selected by the ADCK bit (bit 4) of ADC2.
If the rising clock pulse occurs during the operation, comparison is canceled and restarted. When the
external clock is used for comparison or recomparison, comparison and recomparison cannot be exe
cuted by the program.
(3) End
When the result of the comparison meets the conditions specified by SIFM (bit 1) of ADC1, ADI (bit 3) of
ADC1 is set. At that time, an interrupt request is output when ADIE (bit 2) of ADC2 is 1. If the result of
the operation does not meet the specified conditions, ADI (bit 3) of ADC1 is not set. In this case, check
that ADMV (bit 2) of ADC1 is 0.
The preset contents of the data register are held without loss by the comparison operation.
(4) Continuous start of comparison by external clock
Comparison can be started continuously by providing an external clock based on the comparison time.