參數(shù)資料
型號(hào): MB89498PFV
廠商: FUJITSU LTD
元件分類(lèi): 微控制器/微處理器
英文描述: 8-bit Proprietary Microcontroller CMOS
中文描述: 8-BIT, MROM, 12.5 MHz, MICROCONTROLLER, PQFP100
封裝: PLASTIC, LQFP-100
文件頁(yè)數(shù): 21/57頁(yè)
文件大小: 341K
代理商: MB89498PFV
MB89490 Series
21
The RP indicates the address of the register bank currently in use. The relationship between the pointer contents
and the actual address is based on the conversion rule illustrated below.
The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and
bits for controlling the CPU operations at the time of an interrupt.
H-flag : Set to “1” when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Clear
to “0” otherwise. This flag is for decimal adjustment instructions.
I-flag : Interrupt is allowed when this flag is set to “1”. Interrupt is prohibited when the flag is set to “0”. Clear to
“0” at reset.
IL1, 0 : Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request is higher
than the value indicated by this bit.
IL1
IL0
Interrupt level
High-low
0
0
1
High
Low
0
1
1
0
2
1
1
3
N-flag : Set to “1” if the MSB is set to “1” as the result of an arithmetic operation. Clear to “0” otherwise.
Z-flag : Set to “1” when an arithmetic operation results in “0”. Clear to “0” otherwise.
V-flag : Set to “1” if the complement on 2 overflows as a result of an arithmetic operation. Clear to “0” if the
overflow does not occur.
C-flag : Set to “1” when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Clear to “0”
otherwise. Set to the shift-out value in the case of a shift instruction.
Lower OP codes
RP
Generated addresses
“0”
“0”
“0”
“0”
“0”
“0”
“0”
“1” R4 R3 R2 R1 R0
b2
b1
b0
A15 A14 A13 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Conversion rule for Actual Addresses of the General-purpose Register Area
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