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參數(shù)資料
| 型號： | MB88111PFQ |
| 廠商： | FUJITSU LTD |
| 元件分類： | ADC |
| 英文描述： | A/D Converter (With 24-Channel Input at 10-bit Resolution) |
| 中文描述： | 24-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數(shù)： | 17/26頁 |
| 文件大小： | 169K |
| 代理商： | MB88111PFQ |
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17
MB88111
4. AC Characteristics
(AV
CC
,
V
CC
= +3.5 V to +5.5 V (V
CC
≥
AV
CC
), V
SS
= AGND = 0 V, Ta = –40
°
C to +105
°
C)
Parameter
Symbol
Conditions
Values
Unit
Min.
Max.
CCLK clock cycle time
f
CLK
f
CLK
= 1/f
CLK
800
1200
KHz
Low-level CCLK clock pulse width
t
CKL
—
400
—
ns
High-level CCLK clock pulse width
t
CKH
—
400
—
ns
CCLK clock rise time
t
Cr
—
–
10
ns
CCLK clock fall time
t
Cf
SCK clock cycle time
f
SCK
t
SCK
= 1/f
SCK
400
1200
KHz
Low-level SCK clock pulse width
t
SKL
—
400
—
ns
High-level SCK clock pulse width
t
SKH
—
400
—
ns
SCK clock rise time
t
Sr
—
–
10
ns
SCK clock fall time
t
Sf
SIN setup time
t
SIS
—
50
—
ns
SIN hold time
t
SIH
—
250
—
ns
μ
s
μ
s
ns
μ
s
Command interval
t
COM
CCLK = 1 MHz
4
—
ENDC reset time
t
ENR
See “Load conditions.”
–
1
RSTX pulse width
RSTX
↑ →
SCK
↓
time
SCK
↑ →
CS1
↓
time
SCK
↑ →
CS2X
↑
time
CS1
↑ →
SCK
↓
time
CS2X
↓ →
SCK
↓
time
SOT output delay time (mode A)
t
RSH
—
100
—
t
RSS
—
1
—
t
CSS
—
500
—
ns
t
CSH
—
500
—
ns
t
SODA
See “Load conditions.”
—
300
ns
SOT output delay time (mode B)
ENDC
↑ →
SOT output (mode B)
STC command A/D conversion time
t
SODB
See “Load conditions.”
—
300
ns
t
SOHB
See “Load conditions.”
—
200
ns
μ
s
μ
s
μ
s
μ
s
μ
s
ns
t
STC
CCLK = 1 MHz
—
50
ATC command A/D conversion time
t
SATC
CCLK = 1 MHz
—
50
ATGX setup time
t
SATS
CCLK = 1 MHz
4
—
ATGX hold time
t
SATH
CCLK = 1 MHz
2
—
Port input evaluation time
t
POT
CCLK = 1 MHz
—
10
Port input setup time
t
PTS
—
0
—
Port input hold time
t
PTH
—
0
—
ns
Extended serial HL propagation delay
t
SHL
See “Load conditions.”
—
100
ns
Extended serial LH propagation delay
t
SLH
See “Load conditions.”
—
100
ns
Noise filter width
t
INF
—
15
—
ns
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