參數(shù)資料
型號(hào)： MB86611A
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 98.304M bps, SERIAL COMM CONTROLLER, PQFP100
封裝： 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁(yè)數(shù)： 41/43頁(yè)
文件大小： 480K
代理商： MB86611A
MB86611A
7
ISOCHRONOUS INTERFACE
I/O
I
O
I/O
I
ICLK
IDIR
ILWRE
ID7 - ID0
IV
Clock input pin for Isochronous- Data Interface. (4MHz to 16MHz)
Data Direction Control pin for Isochronous transfer.
When ”0” is input, it clears FIFO and enters ”Transmission” state. Data transmission starts
after asserting ILWRE signal and receiving one packet data specified in the packet header
setting register at address 10h of bank- 0 registers. When ”1” is input, it clears FIFO and
enters ”Receipt” state. However, when there are any packets in process (in transmission), the
device will not be in ”receipt” state until all the packet is transmitted. Receiving 1 packet as-
serts ILWRE signal.
IDIR signal should normally be ”1” (”H”), and should be ”0” (”L”) only when transmitting the
data.
Access Permission Signal output pin for Isochronous- FIFO.
For Transmission state : It becomes ”Active” if FIFO has a space. This signal is negated by
the FIFO state ”Full”. At the negate state of this signal, the device receives the data for a
rising edge of the next ICLK signal. When the Bus- Reset is detected, it is negated after re-
ceiving the data on packet boundary. After the bus reset, this signal is again asserted at the
completion of transmitting one packet data from the FIFO.
For Receipt state: This signal is asserted when one packet is completely received in the
FIFO. It is once negated every time when one packet is read out from the FIFO. When the
FIFO still has packets in it, the signal is again asserted.
Data input/output pins for Isochronous transfer. (MSB:ID7, LSB:ID0)
Enable Signal Input pin for ID7- ID0.
For Transmission state : While this signal is active, the data are fetched into FIFO at the ris-
ing edge of ICLK.
For Receipt state : Making this signal state ”Active” starts to send the data in FIFO to
ID7- ID0. After that, the data changes synchronizing with the rising edge of ICLK.
Name of pin
Function
O
I/O
ICRCE
FP
This signal indicates that data CRC error occurred in the received data.
Time- Stamp Trigger Signal input/output pin.
For transmission state: This is a Time- Stamp Trigger input pin. The MB86611A fetches it’s
internal cycle timer register value by a falling edge of this signal.
For Receipt state : This pin outputs the detection signal that Time- Stamp matched.
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