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參數(shù)資料
| 型號(hào)： | MB86605PMT |
| 元件分類： | 總線控制器 |
| 英文描述： | SCSI BUS CONTROLLER, PQFP144 |
| 封裝： | PLASTIC, LQFP-144 |
| 文件頁數(shù)： | 3/64頁 |
| 文件大?。?/td> | 275K |
| 代理商： | MB86605PMT |
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11
MB86605
(Continued)
4.
PCI Bus Interface Mode
Pin no.
Pin name
I/O
Function
132
DMBHE
(DMUDS)
I
In 80-series mode: This is used to input the BHE signal output by
the DMAC when the upper byte of the DMA
data bus is valid.
In 68-series mode: This is used to input the UDS signal output by
the DMAC when the upper byte of the DMA
data bus is valid.
125
DMA0
I
This is used to input the address data A0 signal output by the
DMAC in the 80-series mode.
In 68-series mode: Connect to power supply pin (VDD).
126
TP
(Transfer
permission)
I
This is used to input DMA-transfer-enabling signals.
When the TP signal is active, the SPC performs the DMA transfer.
When this signal becomes inactive during DMA transfer, the
transfer stops temporarily at the block boundary.
Pin no.
Pin name
I/O
Function
130
PREQ
O
This pin is used to request the bus arbiter for use of the bus.
129
GNT
I
This is the response signal input pin to the REQ signal from the
bus arbiter.
132, 133, 135, 136,
138, 139, 141, 142,
1, 3 to 5, 7, 9 to 11,
26 to 29, 32 to 34, 36,
38, 39, 41, 42, 44,
46 to 48
AD31 to AD0
I/O PCI 32-bit address and data multiplexed pins
143, 13, 24, 37
C/BE3 to C/BE0
I/O Bus command and Byte Enable signals multiplexed pins.
23
PAR
I/O This is an even parity signal pin for the AD31 to AD0 and C/BE3
to C/BE0 signals. This PAR signal becomes valid after one clock.
14
FRAME
I/O This is a frame signal pin that indicates data are transferring on
the bus.
17
TRDY
I/O Data Ready signal of Target side.
15
IRDY
I/O Data Ready signal of Initiator (Bus master) side.
20
STOP
I/O This is a stop request signal to stop the data transfer from target
to master.
19
DEVSEL
I/O Device select pin. While the device is a target, this pin outputs the
select signal that indicates the self device is selected. While the
device is a master this pin functions as an input pin to indicate
that a device on the bus is selected.
144
IDSEL
I
This is a chip select signal that indicates the configuration access.
126
PCLK
I
PCI bus clock input pin. The maximum clock frequency is 33
MHz.
22
PERR
I/O Data parity error input and output pin.
125
SERR
OD Address parity error output pin.
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