參數(shù)資料
型號(hào)： MB86605PMT
元件分類： 總線控制器
英文描述： SCSI BUS CONTROLLER, PQFP144
封裝： PLASTIC, LQFP-144
文件頁(yè)數(shù)： 2/64頁(yè)
文件大?。?/td> 275K
代理商： MB86605PMT
10
MB86605
(Continued)
3.
16-Bit Bus Mode – DMA Interface
(Continued)
Pin no.
Pin name
I/O
Function
51, 52, 55 to 57
A4 to A0
IU These are used to input addresses for selecting the Internal
registers.
46
RD (R/W)
I
In 80-series mode: This is used to input the read strobe signal for
reading data from the SPC to the MPU.
In 68-series mode: This is used to input the R/W control signal for
reading and writing data from the MPU to the
SPC.
44
WR (LDS)
I
In 80-series mode: This is used to input the write strobe signal for
writing data from the MPU to the SPC.
In 68-series mode: This is used to input the LDS signal output by
the MPU when the lower byte of the data bus
is valid.
42
BHE (UDS)
I
In 80-series mode: This is used to input the BHE signal output by
the MPU when the upper byte of the data bus
is valid.
In 68-series mode: This is used to input the UDS signal output by
the MPU when the upper byte of the data bus
is valid.
Pin no.
Pin name
I/O
Function
130
DREQ
O This is used to output DMA transfer request signals to the DMAC.
DMA data transfer between the SPC and memory is requested.
129
DACK
I
This is used to input DMA-enabling signals from the DMAC.
When the DMA enabling signal is active, DMA reading and writing
are executed.
138, 139, 141 to 144, 1, 3
136
DMD15 to 8
UDMDP
I/O Upper byte and parity of DMA data bus
When CS1 input valid: The MPU data bus is directly connected.
When 80-series mode: The 2nd data is input/output.
When 68-series mode: The 1st data is input/output.
4, 5, 7, 9 to 11, 13, 14
15
DMD7 to 0
LDMDP
I/O Lower byte and parity of DMA data bus
When CS1 input valid: The MPU data bus is directly connected.
When 80-series mode: The 1st data is input/output.
When 68-series mode: The 2nd data is input/output.
135
IORD
(DMR/W)
I
In 80-series mode: This is used to input the IORD or RD signal for
outputting data from the SPC to the DMA bus.
In 68-series mode: This is used to input the R/W control signal for
outputting and inputting data from the DMAC
to the SPC.
133
IOWR
(DMLDS)
I
In 80-series mode: This is used to input the IOWR or WR signal
for inputting data from the DMA bus to the
SPC.
In 68-series mode: This is used to input the LDS signal output by
the DMAC when the lower byte of the DMA
data bus is valid.
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