參數(shù)資料
型號： MB86603
廠商： FUJITSU LTD
元件分類： 總線控制器
英文描述： Communication Control SCSI-II Protocol Controller(通信控制SCSI-II協(xié)議控制器)
中文描述： SCSI BUS CONTROLLER, PQFP176
封裝： PLASTIC, SQFP-176
文件頁數(shù)： 12/58頁
文件大?。?/td> 401K
代理商： MB86603
12
MB86603
3. DMA Interface
Like the MPU interface, the DMA interface has input/output signals for the 68 series and 80 series
.
(Continued)
Pin No.
Pin Symbol*
Pin Name
I/O
Function
82
DREQ
DMA Request
O
This is used for output of DMA transfer request signals to
the DMA controller.
A request is made for data transfer between the SPC and the
memory over the DMA bus.
The signal is Active High.
81
DACK
DMAAcknowledge
I
This is used for input of DMA acknowledge signals from
the DMA controller.
When this input pin is active, the DMA cycle (read/write) is
executed.
The signal is Active Low.
74 to 72,
70 to 66
DMD15 to
DMD8
DMA Data 15 to
DMA Data 8
I/O
These are used for input and output of the upper-byte and
parity signals of the DMA data bus.
When the CS1 input is valid, these pins are connected directly
to the MPU bus.
76
UDMDP
Upper DMA
Data Parity
64 to 59,
57, 56
DMD7 to
DMD0
DMA Data 7 to
DMA Data 0
I/O
These are used for input and output of the lower-byte and
parity signals of the DMA data bus.
When the CS1 input is valid, these pins are connected directly
to the MPU bus.
54
LDMDP
Lower DMA
Data Parity
50
IORD
(DMR/W)
I/O Read (DMA
Read/Write)
I
In the 80-series mode, this is used for input of signals
(IORD or RD) for outputting data from the SPC to the DMA
bus.
The signal is Active Low.
In the 68-series mode, this is used for input of control signals
(DMR/W) for inputting and outputting data from the DMA con-
troller to the SPC.
The signal is Active High for output and Active Low for input.
51
IOWR
(DMLDS)
I/O Write (DMA
Lower Data
Strobe)
I
In the 80-series mode, this is used for input of signals
(IOWR or WR) for inputting data from the DMA bus to the
SPC.
In the 68-series mode, this is used for input of LDS signals out-
put by the DMA controller when the lower bytes of the DMA
data bus are valid.
The signal is Active Low in both modes.
79
DMBHE
(DMUDS)
DMA Bus
High Enable
(Upper Data
Strobe)
I
In the 80-series mode, this is used for input of BHE
signals output by the DMA controller when the upper
bytes of the DMA data bus are valid.
In the 68-series mode, this is used for input of UDS
signals output by the DMA controller when the upper
bytes of the DMA data bus are valid.
The signal is Active Low in both modes.
53
DMA0
DMA Address 0
I
In the 80-series mode, this is used for input of address
data A0 signals output by the DMA controller.
In the 68-series mode, this is connected to the power supply
(V
DD
).
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