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參數(shù)資料
| 型號： | MB86435PFV |
| 廠商： | FUJITSU LTD |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | RES 360 OHM 1/16W 5% 0402 SMD |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP64 |
| 封裝： | PLASTIC, LQFP-64 |
| 文件頁數(shù)： | 4/36頁 |
| 文件大小： | 610K |
| 代理商： | MB86435PFV |
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4
MB86435
(Continued)
Pin No.
Symbol
I/O
A/D
Description
21
LO2
O
D
External control latch output pin. Outputs value D
2
of address 1000. CMOS
interface.
22
LO3
O
D
External control latch output pin. Outputs value D
3
of address 1000. CMOS
interface.
23
TCLK
I
D
Tone generator clock input pin. Can be used as a tone CLK signal by using
address 1110 D4D3 to subdivide the internal clock signal by factors of 1/1,
1/2, 1/4. CMOS interface.
24
TONC
I
D
Tone generator cycle control input pin. CMOS interface. Hlevel signal
outputs tone.
25
LED
O
D
Ring LED control output pin. CMOS interface.
26
DSCK
I/O
A
Can be connected to EXSD or TAUD by switching bus.
27
EXSD
I/O
A
Can be connected to DSCK or TAUD by switching bus.
28
TAUD
I/O
A
Can be connected to EXSD or DSCK by switching bus.
29
DSDT
I
A
Can be connected to RAUD by switching bus.
30
TONEO
O
A
Tone signal output pin.
31
RAUD
O
A
Output pin for external speaker, or audio test signal. Can be connected to
DSDT by switching paths.
32
VDDSP1
P
A
Speaker amp power supply pin. To be set within range 2.7 to 3.6 V.
Earphone speaker amp output pin. Capable of 2 mW output at 32
load.
Receiver speaker amp output pin. Internally connected to EAR and BTL.
Maximum output of 6.4 mW can be obtained at 32
load by connecting
speaker between EAR and XEAR.
33
JEAR
O
34
XEAR
O
A
35
EAR
O
A
Receiver speaker amp output pin. Connected to XEAR and BTL.
36
SPG1
G
A
Speaker amp ground pin. To be set to 0 V.
37
SPG2
G
A
Speaker amp ground pin. To be set to 0 V.
38
XTONE
O
A
Speaker amp tone output pin. Internally connected to TONE and BLT.
Maximum output of 10 mW can be obtained at 25
load by connecting
speaker between TONE and XTONE.
39
TONE
O
A
Speaker amp tone output pin. When speaker amp is not used for tone,
TONE should be shorted to IMTON.
40
IMTON
I
A
Speaker drive inverted (–) signal input pin. Can be used to adjust gain by
connecting resistance to TONE and IMTON.
41
VDDSP2
P
A
Speaker amp power supply pin. To be set within range 2.7 to 3.6 V.
42
BBI
O
A
AMP3 output pin. Should be included in HPF together with IM3, to prevent
DC offset from entering speakers.
43
IM3
I
A
AMP3 inverted (–) signal input pin.
44
BTO
O
A
Receiving volume adjustment circuit output pin.
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