參數(shù)資料
型號: MB84VD22183EA-85PBS
元件分類: 存儲器
英文描述: SPECIALTY MEMORY CIRCUIT, PBGA71
封裝: PLASTIC, BGA-71
文件頁數(shù): 57/64頁
文件大?。?/td> 1177K
代理商: MB84VD22183EA-85PBS
MB84VD2218XEA/H/2219XEA/H-70/85/90
60
s
s ERASE AND PROGRAMMING PERFORMANCE (Flash)
s
s DATA RETENTION CHARACTERISTICS (SRAM)
Note : tRC : Read cycle time
CE1s Controlled Data Retention Mode *1
Parameter
Limits
Unit
Comment
Min
Typ
Max
Sector Erase Time
110
s
Excludes programming time
prior to erasure
Byte Programming Time
8
300
s
Excludes system-level
overhead
Word Programming Time
16
360
s
Excludes system-level
overhead
Chip Programming Time
100
s
Excludes system-level
overhead
Erase/Program Cycle
100,000
cycle
Parameter
Symbol
Value
Unit
Min
Typ
Max
Data Retention Supply Voltage
VDH
1.5
3.3
V
Standby Current
VDH
= 3.0 V
IDDS2
1.5
7
A
Chip Deselect to Data Retention Mode Time
tCDR
0
ns
Recovery Time
tR
tRC
ns
DATA RETENTION MODE
*2
tR
tCDR
VCCS
0.2 V
VCCs
VIH
VDH
CE1s
2.7 V
GND
*1: In CE1s controlled data retention mode, input level of CE2s should be fixed VCCs to VCCs
0.2 V or VSS
to 0.2 V during data retention mode. Other input and input/output pins can be used between
0.3 V to
VCCs
+ 0.3 V.
*2: When CE1s is operating at the VIH Min level, the standby current is given by ISB1s during the transition of
VCCs from 3.3 V to VIH Min level.
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