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參數資料
| 型號： | MB81V16400B-50 |
| 廠商： | Fujitsu Limited |
| 英文描述： | 4 M ×4 BITS Fast Page Mode Dynamic RAM(CMOS 4 M ×4 位快速頁面存取模式RAM) |
| 中文描述： | 4米× 4位快速頁面模式動態(tài)RAM（的CMOS 4米× 4位快速頁面存取模式的RAM） |
| 文件頁數： | 1/27頁 |
| 文件大?。?/td> | 477K |
| 代理商： | MB81V16400B-50 |
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DS05-11314-1E
FUJITSU SEMICONDUCTOR
DATA SHEET
MEMORY
CMOS
4 M
FAST PAGE MODE DYNAMIC RAM
MB81V16400B-50/-60
×
4 BITS
CMOS 4,194,304
×
4 BITS Fast Page Mode Dynamic RAM
I
DESCRIPTION
The Fujitsu MB81V16400B is a fully decoded CMOS Dynamic RAM (DRAM) that contains 16,777,216 memory
cells accessible in 4-bit increments. The MB81V16400B features a “fast page” mode of operation whereby high-
speed random access of up to 1,024-bits of data within the same row can be selected. The MB81V16400B DRAM
is ideally suited for mainframe, buffers, hand-held computers video imaging equipment, and other memory
applications where very low power dissipation and high bandwidth are basic requirements of the design. Since
the standby current of the MB81V16400B is very small, the device can be used as a non-volatile memory in
equipment that uses batteries for primary and/or auxiliary power.
The MB81V16400B is fabricated using silicon gate CMOS and Fujitsu’s advanced four-layer polysilicon and two-
layer aluminum process. This process, coupled with advanced stacked capacitor memory cells, reduces the
possibility of soft errors and extends the time interval between memory refreshes. Clock timing requirements for
the MB81V16400B are not critical and all inputs are LVTTL compatible.
I
PRODUCT LINE & FEATURES
Parameter
MB81V16400B-50
50 ns max.
90 ns min.
25 ns max.
13 ns max.
35 ns min.
324 mW max.
3.6 mW max. (TTL level) / 1.8 mW max. (CMOS level)
MB81V16400B-60
60 ns max.
110 ns min.
30 ns max.
15 ns max.
40 ns min.
270 mW max.
RAS Access Time
Random Cycle Time
Address Access Time
CAS Access Time
Fast Page Mode Cycle Time
Low Power
Dissipation
Operating Current
Standby Current
4,194,304 words
×
4 bits organization
Silicon gate, CMOS, Advanced Capacitor Cell
All input and output are LVTTL compatible
4096 refresh cycles every 65.6 ms
Early Write or OE controlled write capability
RAS only, CAS-before-RAS, or Hidden
Refresh
Fast page Mode, Read-Modify-Write
capability
On chip substrate bias generator for high
performance
相關PDF資料 |
PDF描述 |
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| MB81V16400B-60 | 4 M ×4 BITS Fast Page Mode Dynamic RAM(CMOS 4 M ×4 位快速頁面存取模式RAM) |
| MB81V16405A-60 | 4 M ×4 BIT Hyper Page Mode Dynamic RAM(CMOS 4 M ×4 位超級頁面存取模式動態(tài)RAM) |
| MB81V16405A-70 | 4 M ×4 BIT Hyper Page Mode Dynamic RAM(CMOS 4 M ×4 位超級頁面存取模式動態(tài)RAM) |
| MB81V17405A-60 | 4 M ×4 BIT Hyper Page Mode Dynamic RAM(CMOS 4 M ×4 位超級頁面存取模式動態(tài)RAM) |
| MB81V17405A-70 | 4 M ×4 BIT Hyper Page Mode Dynamic RAM(CMOS 4 M ×4 位超級頁面存取模式動態(tài)RAM) |
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