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參數(shù)資料
| 型號： | MB81V16405A-60 |
| 廠商： | Fujitsu Limited |
| 英文描述： | 4 M ×4 BIT Hyper Page Mode Dynamic RAM(CMOS 4 M ×4 位超級頁面存取模式動態(tài)RAM) |
| 中文描述： | 4米× 4位超頁模式動態(tài)RAM（的CMOS 4米× 4位超級頁面存取模式動態(tài)內(nèi)存） |
| 文件頁數(shù)： | 1/30頁 |
| 文件大小： | 549K |
| 代理商： | MB81V16405A-60 |
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DS05-11302-1E
FUJITSU SEMICONDUCTOR
DATA SHEET
MEMORY
CMOS
4 M
HYPER PAGE MODE DYNAMIC RAM
×
4 BITS
MB81V16405A-60/-70
CMOS 4,194,304
×
4 BITS Hyper Page Mode Dynamic RAM
I
DESCRIPTION
The Fujitsu MB81V16405A is a fully decoded CMOS Dynamic RAM (DRAM) that contains 16,777,216 memory
cells accessible in 4-bit increments. The MB81V16405A features a “hyper page” mode of operation whereby high-
speed random access of up to 1,024
×
4 bits of data within the same row can be selected. The MB81V16405A
DRAM is ideally suited for mainframe, buffers, hand-held computers video imaging equipment, and other memory
applications where very low power dissipation and high bandwidth are basic requirements of the design. Since
the standby current of the MB81V16405A is very small, the device can be used as a non-volatile memory in
equipment that uses batteries for primary and/or auxiliary power.
The MB81V16405A is fabricated using silicon gate CMOS and Fujitsu’s advanced four-layer polysilicon and two-
layer aluminum process. This process, coupled with advanced stacked capacitor memory cells, reduces the
possibility of soft errors and extends the time interval between memory refreshes. Clock timing requirements for
the MB81V16405A are not critical and all inputs are LVTTL compatible.
I
PRODUCT LINE & FEATURES
Parameter
MB81V16405A-60
60 ns max.
104 ns min.
30 ns max.
15 ns max.
25 ns min.
288 mW max.
7.2 mW max. (LVTTL level) / 3.6 mW max. (CMOS level)
MB81V16405A-70
70 ns max.
124 ns min.
35 ns max.
17 ns max.
30 ns min.
252 mW max.
RAS Access Time
Random Cycle Time
Address Access Time
CAS Access Time
Hyper Page Mode Cycle Time
Low Power
Dissipation
Operating Current
Standby Current
4,194,304 words
×
4 bits organization
Silicon gate, CMOS, Advanced stacked
Capacitor Cell
All input and output are LVTTL compatible
4,096 refresh cycles every 65.6 ms
Early write or OE controlled write capability
RAS-only, CAS-before-RAS, or Hidden
Refresh
Hyper Page Mode, Read-Modify-Write
capability
On chip substrate bias generator for high
performance
相關(guān)PDF資料 |
PDF描述 |
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| MB81V16405A-70 | 4 M ×4 BIT Hyper Page Mode Dynamic RAM(CMOS 4 M ×4 位超級頁面存取模式動態(tài)RAM) |
| MB81V17405A-60 | 4 M ×4 BIT Hyper Page Mode Dynamic RAM(CMOS 4 M ×4 位超級頁面存取模式動態(tài)RAM) |
| MB81V17405A-70 | 4 M ×4 BIT Hyper Page Mode Dynamic RAM(CMOS 4 M ×4 位超級頁面存取模式動態(tài)RAM) |
| MB81V17800A-60 | CMOS 2 M ×8 BIT Fast Page Mode DRAM(CMOS 2 M ×8 位快速頁面存取模式動態(tài)RAM) |
| MB81V17800A-60L | CMOS 2 M ×8 BIT Fast Page Mode DRAM(CMOS 2 M ×8 位快速頁面存取模式動態(tài)RAM) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
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