參數(shù)資料
型號: MB81F643242C-60
廠商: Fujitsu Limited
英文描述: 4 X 512 K X 32 BIT SYNCHRONOUS DYNAMIC RAM
中文描述: 4 × 512 kX的32位同步動(dòng)態(tài)隨機(jī)存儲(chǔ)器
文件頁數(shù): 48/56頁
文件大?。?/td> 1001K
代理商: MB81F643242C-60
48
MB81F643242C-60/-70/-10
Advanced Info (AE0.1E)
AC SPECIFICATION
TIMING DIAGRAMS
Parameter
Description
Minimum
Maximum
Units
t
TS
Test mode entry set up time
10
ns
t
TH
Test mode entry hold time
10
ns
t
EPD
Test mode exit to power on sequence delay time
10
ns
t
TLZ
Test mode output in Low-Z time
0
ns
t
THZ
Test mode output in High-Z time
0
20
ns
t
TCA
Test mode access time from control signals
(output enable & chip select)
40
ns
t
TIA
Test mode Input access time
20
ns
t
TOH
Test mode Output Hold time
0
ns
t
ETD
Test mode entry to test delay time
10
ns
t
TIH
Test mode input hold time
30
ns
TIMING DIAGRAM – 1 : POWER-UP TIMING DIAGRAM
V
DD
CS
CKE
CAS
*3
100
μ
s Pause Time
Test Mode Entry Point
Notes:
*1. SCITT is enabled if CS = L, CKE = L, CAS = L at just power on.
*2. All output buffers maintains in High-Z state regardless of the state of control signals as long as
the above timing is maintained.
*3. CAS must not be brought from High to Low.
*2
*1
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