- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377885 > MB814800-70 (Fujitsu Limited) CMOS 512K ×8 BIT FAST PAGE MODE DYNAMIC RAM(CMOS 512K ×8位快速頁面存取模式動態(tài)RAM) PDF資料下載
參數(shù)資料
| 型號： | MB814800-70 |
| 廠商： | Fujitsu Limited |
| 英文描述： | CMOS 512K ×8 BIT FAST PAGE MODE DYNAMIC RAM(CMOS 512K ×8位快速頁面存取模式動態(tài)RAM) |
| 中文描述： | 的CMOS為512k × 8位快速頁面模式的動態(tài)隨機存儲器（的CMOS為512k × 8位快速頁面存取模式動態(tài)內(nèi)存） |
| 文件頁數(shù)： | 22/26頁 |
| 文件大小： | 327K |
| 代理商： | MB814800-70 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁當(dāng)前第22頁第23頁第24頁第25頁第26頁
22
MB814800-60/MB814800-70
CAS
Fig. 16 – CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE
(At recommended operating conditions unless otherwise noted.)
Note: Assumes that CAS-before-RAS refresh counter test cycle only.
V
IH
V
IL
V
IH
V
IL
RAS
A
0
to A
9
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
WE
DQ
(Input)
OE
DESCRIPTION
A special timing sequence using the CAS-before-RAS refresh counter test cycle provides a convenient method to verify the
functionality of CAS-before-RAS refresh circuitry. If, after a CAS-before-RAS refresh cycle. CAS makes a transition from High to
Low while RAS is held Low, read and write operations are enabled as shown above. Row and column addresses are defined as
follows:
Row Address: Bits A
0
through A
9
are defined by the on-chip refresh counter.
Column Address: Bits A
0
through A
8
are defined by latching levels on A
0
-A
8
at the second falling edge of CAS.
The CAS-before-RAS Counter Test procedure is as follows;
1) Initialize the internal refresh address counter by using 8 RAS only refresh cycles.
2) Use the same column address throughout the test.
3) Write “0” to all 1024 row addresses at the same column address by using normal write cycles.
4) Read “0” written in procedure 3) and check; simultaneously write “1” to the same addresses by using CAS-before-RAS
refresh counter test (read-modify-write cycles). Repeat this procedure 1024 times with addresses generated by the
internal refresh address counter.
5) Read and check data written in procedure 4) by using normal read cycle for all 1024 memory locations.
6) Reverse test data and repeat procedures 3), 4), and 5).
DQ
(Output)
“H” or
Valid Data
HIGH-Z
HIGH-Z
t
OEH
HIGH-Z
t
DHR
VALID DATA IN
COLUMN ADDRESS
t
CSR
t
RP
t
CP
t
RCS
t
FCAH
t
ASC
t
CWL
t
CHR
t
FRSH
t
FCAS
t
RWL
t
FCWD
t
WCR
t
FCSH
t
RAL
t
DH
t
WP
t
DS
t
DZC
t
OED
t
FCAC
t
ON
t
OEA
t
DZO
t
OEZ
CAS to WE Delay Time
Parameter
Unit
Min.
Max.
ns
No.
Min.
Max.
90
—
55
55
Symbol
91
30
—
—
ns
30
Column Address Hold Time
92
CAS Pulse width
93
RAS Hold Time
80
—
—
ns
80
55
—
—
ns
55
94
55
—
—
ns
55
—
—
ns
85
—
85
CAS Hold Time
95
MB814800-60
MB814800-70
Access Time from CAS
t
FCAC
t
FCAH
t
FCWD
t
FCAS
t
FCSH
t
FRSH
t
AR
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MB81F643242C | 4 X 512 K X 32 BIT SYNCHRONOUS DYNAMIC RAM |
| MB81F643242C-10 | 4 X 512 K X 32 BIT SYNCHRONOUS DYNAMIC RAM |
| MB81F643242C-60 | 4 X 512 K X 32 BIT SYNCHRONOUS DYNAMIC RAM |
| MB81F643242C-70 | 4 X 512 K X 32 BIT SYNCHRONOUS DYNAMIC RAM |
| MB81G83222-012 | CMOS 2×128K ×32 Synchronous GRAM(CMOS 2×128K ×32位同步圖形RAM) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB8148L-70 | 制造商:FUJITSU 功能描述: |
| MB8151 | 制造商:n/a 功能描述:8151 |
| MB8167-A55 | 制造商:FUG 功能描述:8167A-55 |
| MB8167A-55 | 制造商:Fuji Electric 功能描述:MB8167A-55 制造商:FUJITSU 功能描述:MB8167A-55 |
| MB8167A70 | 制造商:FUJI 功能描述:* |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。