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參數(shù)資料
| 型號： | MB8117800A-70 |
| 廠商： | Fujitsu Limited |
| 英文描述： | CMOS 2 M ×8BIT Fast Page Mode DRAM(CMOS 2 M ×8 位快速頁面存取模式動態(tài)RAM) |
| 中文描述： | 的CMOS 2米× 8位快速頁面模式的DRAM的CMOS（2米× 8位快速頁面存取模式動態(tài)內(nèi)存） |
| 文件頁數(shù)： | 5/25頁 |
| 文件大?。?/td> | 474K |
| 代理商： | MB8117800A-70 |
5
MB8117800A-60/MB8117800A-70
I
RECOMMENDED OPERATING CONDITIONS
* :Undershoots of up to –2.0 volts with a pulse width not exceeding 20ns are acceptable.
I
FUNCTIONAL OPERATION
ADDRESS INPUTS
Twenty-one input bits are required to decode any eight of 16,777,216 cell addresses in the memory matrix.
Since only eleven address bits (A0 to A10) are available, the row and column inputs are separately strobed by
RAS and CAS as shown in Figure 1. First, eleven row address bits are input on pins A0-through-A10 and latched
with the row address strobe (RAS) then, ten column address bits are input and latched with the column address
strobe (CAS). Both row and column addresses must be stable on or before the falling edge of RAS and CAS,
respectively. The address latches are of the flow-through type; thus, address information appearing after t
RAH
(min) + t
T
is automatically treated as the column address.
WRITE ENABLE
The read or write mode is determined by the logic state of WE. When WE is active Low, a write cycle is initiated;
when WE is High, a read cycle is selected. During the read mode, input data is ignored.
DATA INPUT
Input data is written into memory in either of three basic ways-an early write cycle, an OE (delayed) write cycle,
and a read-modify-write cycle. The falling edge of WE or CAS, whichever is later, serves as the input data-latch
strobe. In an early write cycle, the input data (DQ
1
-DQ
8
) is strobed by CAS and the setup/hold times are referenced
to CAS because WE goes Low before CAS. In a delayed write or a read-modify-write cycle, WE goes Low after
CAS; thus, input data is strobed by WE and all setup/hold times are referenced to the write-enable signal.
DATA OUTPUT
The three-state buffers are TTL compatible with a fanout of two TTL loads. Polarity of the output data is identical
to that of the input; the output buffers remain in the high-impedance state until the column address strobe goes
Low. When a read or read-modify-write cycle is executed, valid outputs are obtained under the following
conditions:
t
RAC
:
from the falling edge of RAS when t
RCD
(max) is satisfied.
t
CAC
:
from the falling edge of CAS when t
RCD
is greater than t
RCD
(max).
t
AA
:
from
column address input when t
RAD
is greater than t
RAD
(max).
t
OEA
:
from the falling edge of OE when OE is brought Low after t
RAC
, t
CAC
, or t
AA
.
The data remains valid until either CAS or OE returns to a High logic level. When an early write is executed, the
output buffers remain in a high-impedance state during the entire cycle.
FAST PAGE MODE OF OPERATION
The fast page mode of operation provides faster memory access and lower power dissipation. The fast page
mode is implemented by keeping the same row address and strobing in successive column addresses. To satisfy
these conditions, RAS is held Low for all contiguous memory cycles in which row addresses are common. For
each fast page of memory, any of 1,024 x 8-bits can be accessed and, when multiple MB8117800As are used,
CAS is decoded to select the desired memory fast page. Fast page mode operations need not be addressed
sequentially and combinations of read, write, and/or read-modify-write cycles are permitted.
Parameter
Notes
Symbol
Min.
Typ.
Max.
Unit
Ambient
Operating Temp
Supply Voltage
V
CC
V
SS
V
IH
4.5
0
2.4
5.0
0
—
5.5
0
6.5
V
0
°
C to + 70
°
C
Input High Voltage, all inputs
V
Input Low Voltage, all inputs*
V
IL
–3.0
—
0.8
V
1
1
1
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