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參數(shù)資料
| 型號： | MB8117800A-70 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 2 M X 8 BIT FAST PAGE MODE DYNAMIC RAM |
| 中文描述： | 2的MX 8位快速頁面模式動態(tài)隨機(jī)存儲器 |
| 文件頁數(shù)： | 13/27頁 |
| 文件大?。?/td> | 580K |
| 代理商： | MB8117800A-70 |
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13
MB8117800A-60/-70
t
RC
t
RAS
t
AR
t
CRP
t
CSH
t
RCD
t
RSH
t
RP
t
CAS
t
CDD
t
OEL
t
RAL
t
CAL
t
CAH
t
ASC
t
RAD
t
RAH
t
ASR
t
RCS
t
RRH
t
RCH
t
OH
t
OFF
t
AA
t
CAC
t
RAC
t
DZC
t
ON
t
OEA
t
OEZ
t
OH
t
OED
t
ON
t
DZO
ROW ADD
COLUMN ADD
HIGH-Z
A
0
to A
10
CAS
V
IH
V
IL
V
IH
V
IL
WE
V
OH
V
OL
RAS
V
IH
V
IL
V
IH
V
IL
DQ
(Output)
V
IH
V
IL
DQ
(Input)
V
IH
V
IL
OE
“H” or “L”
DESCRIPTION
To implement a read operation, a valid address is latched in by the RAS and CAS address strobes and with WE set to a High level
and OE set to a low level, the output is valid once the memory access time has elapsed. The access time is determined by RAS(t
RAC
),
CAS(t
CAC
), OE(t
OEA
) or column addresses (t
AA
) under the following conditions:
If t
RCD
> t
RCD
(max), access time = t
CAC
.
If t
RAD
> t
RAD
(max), access time = t
AA
.
If OE is brought Low after t
RAC
, t
CAC
, or t
AA
(whichever occurs later), access time = t
OEA
.
However, if either CAS or OE goes High, the output returns to a high-impedance state after t
OH
is satisfied.
Fig. 5 – READ CYCLE
HIGH-Z
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