參數(shù)資料
型號： MB8116165A-70
廠商： Fujitsu Limited
英文描述： CMOS 1M ×16 BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×16 位超級頁面存取模式動態(tài)RAM)
中文描述： 的CMOS 100萬× 16位的超頁模式動態(tài)RAM的CMOS（100萬× 16位超級頁面存取模式動態(tài)內(nèi)存）
文件頁數(shù)： 26/30頁
文件大小： 376K
代理商： MB8116165A-70
26
MB8116165A-60/MB8116165A-70
DESCRIPTION
A special timing sequence using the CAS-before-RAS refresh counter test cycle provides a convenient method to verify the function
of CAS-before-RAS refresh circuitry. If a CAS-before-RAS refresh cycle CAS makes a transition from High to Low while RAS is
held Low, read and write operations are enabled as shown above. Row and column addresses are defined as follows:
Row Address: Bits A
0
through A
11
are defined by the on-chip refresh counter.
Column Address: Bits A
0
through A
7
are defined by latching levels on A
0
-A
7
at the second falling edge of CAS.
The CAS-before-RAS Counter Test procedure is as follows ;
1) Initialize the internal refresh address counter by using 8 RAS only refresh cycles.
2) Use the same column address throughout the test.
3) Write “0” to all 4096 row addresses at the same column address by using normal write cycles.
4) Read “0” written in procedure 3) and check; simultaneously write “1” to the same addresses by using CAS-before-RAS
refresh counter test (read-modify-write cycles). Repeat this procedure 4096 times with addresses generated by the
internal refresh address counter.
5) Read and check data written in procedure 4) by using normal read cycle for all 4096 memory locations.
6) Reverse test data and repeat procedures 3), 4), and 5).
Fig. 19 – CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE
DQ
(Input)
DQ
(Output)
RAS
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
LCAS
or
UCAS
WE
A
0
to A
11
V
OH
V
OL
V
IH
V
IL
OE
(At recommended operating conditions unless otherwise noted.)
Note: Assumes that CAS-before-RAS refresh counter test cycle only.
t
CSR
“H” or ”L”
Valid Data
t
RP
t
CP
t
RCS
t
FCAH
t
ASC
t
WP
t
CHR
t
FRSH
t
FCWD
t
DH
t
DS
t
DZC
t
OED
t
ON
t
OEA
t
DZO
t
OEZ
t
OEH
VALID DATA IN
COLUMN ADDRESSES
t
FCAC
HIGH-Z
HIGH-Z
t
FCAS
HIGH-Z
t
CWL
t
RWL
Parameter
Unit
Min.
Max.
ns
No.
Min.
Max.
—
—
55
50
Symbol
35
—
—
ns
35
71
72
73
77
—
—
ns
70
99
—
—
ns
90
99
—
—
ns
90
MB81V16165A-60
MB81V16165A-70
Access Time from CAS
Column Address Hold Time
CAS to WE Delay Time
CAS Pulse width
RAS Hold Time
70
69
t
FCAC
t
FCAH
t
FCWD
t
FCAS
t
FRSH
相關(guān)PDF資料
PDF描述
MB8116165B-50 1 M ×16 BIT Hyper Page Mode Dynamic RAM(CMOS 1 M ×16位超級頁面存取模式動態(tài)RAM)
MB8116165B-60 1 M ×16 BIT Hyper Page Mode Dynamic RAM(CMOS 1 M ×16位超級頁面存取模式動態(tài)RAM)
MB8116400A-50 CMOS 4 M ×4 BIT Fast Page Mode DRAM(CMOS 4 M ×4 位快速頁面存取模式動態(tài)RAM)
MB8116400A-60 CMOS 4 M ×4 BIT Fast Page Mode DRAM(CMOS 4 M ×4 位快速頁面存取模式動態(tài)RAM)
MB8116400A-70 CMOS 4 M ×4 BIT Fast Page Mode DRAM(CMOS 4 M ×4 位快速頁面存取模式動態(tài)RAM)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MB8116E 制造商:FUJITSU 功能描述: 制造商:FUJITSU 功能描述:8116E
MB8117800A-60 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2 M X 8 BIT FAST PAGE MODE DYNAMIC RAM
MB8117800A-70 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2 M X 8 BIT FAST PAGE MODE DYNAMIC RAM
MB812 功能描述:ACCY MOUNT BMM 3/4 58A RoHS:是 類別:RF/IF 和 RFID >> RF配件 系列:* 標(biāo)準(zhǔn)包裝:1 系列:*
MB812.833 功能描述:ACCY MOUNT BMM 3/4 58A RoHS:是 類別:RF/IF 和 RFID >> RF配件 系列:* 標(biāo)準(zhǔn)包裝:1 系列:*
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*