參數(shù)資料
型號: MB6021A
廠商: Fujitsu Limited
英文描述: PCM Coders/Decoders(脈沖編碼器/解碼器)
中文描述: 的PCM編碼器/解碼器(脈沖編碼器/解碼器)
文件頁數(shù): 6/20頁
文件大小: 308K
代理商: MB6021A
6
MB6021A/MB6022A
I
FUNCTIONAL DESCRIPTION
Figure 1 shows a simplifed block diagram of MB6021A and MB6022A.
The Transmit Section in the upper-half of the block diagram is comprised of an input gain amplifier, an anti-aliasing
filter (Anti-Alias), a band-pass filter (COS, LPT, and HPF), and a compressing coder (Coder). An auto-zero circuit
(AZ) is also included in this section. The Receive Section in the lower half of the block diagram is comprised of an
expanding decoder (Decoder) and a low-pass filter (LPF).
Transmit Section
The Transmit Section receives analog signals that are input to an operational amplifier to provide gain adjustment.
The signal from the op amp is transmitted to a second-order analog anti-aliasing filter (Anti-Alias). This filter provides
attenuation of 40 dB (typical) at the 256 kHz effective clock frequency of the switched capacitor cosine filter (COS).
From the cosine filter, the signals enter a fifth-order low-pass filter (LPF) clocked at 128 kHz. From the LPF, the
signals pass into a third-order high-pass filter (HPF) clocked at 128 kHz. The resulting band-pass characteristics
meet both the D3/D4 specification and the CCIT G. 712 recommendation. The output of the high-pass filter is then
sampled by the coder (Coder) at 8 kHz. This coder transforms the analog signals into 8-bit words using compression
law. The encoded PCM data is then output serially from the Output Register at a frequency determined by the external
clock, 64 kHz to 3.152 MHz. An auto-zero circuit (AZ) is utilized for DC offset correction.
Receive Section
The Receive Section’s Input Register filter smooths the decoded signals and corrects for SinX/X attenuation caused
by the 8 kHz sample and hold operation. The decoder reconstructs the analog signals from the PCM data using
expansion law. The output from the decoder is transmitted to a fifth-order low-pass filter (LPF). This LPF smooths
the decoded signals and corrects them for the SinX/X attenuation due to the 8 kHz sampling and holding operation.
Internal Clocks
Two independent phase locked loops (PLLs) generate internal clocks for the Transmit and Receive Sections from
the respective synchronization clocks (XSYNC and RSYNC).
I
Analog Loopback Mode
OPERATING MODES
The Analog Loopback Mode allows all decoding and coding functions to be exercised without using the analog
input (A
IN
) and analog output (A
OUT
). In this mode, a digital input signal is decoded and internally routed to the
transmit filters. The output is available from the digital output (D
ground (AG) level. The Analog Loopback Mode is selected by connecting the PD/L input to the negative supply
voltage (
Vs).
Power-down Mode
OUT
). The analog output (A
OUT
) is forced to the analog
Two Power-down Modes are provided. The Transmit and Receive Sections independently go into power-down
operation in the absence of the respective synchronization clocks (XSYNC and RSYNC). If the external power down
input (PD/L) is connected to a TTL low level, both the Transmit and Receive Sections are powered down regardless
of the synchronization clocks. During power-down operation, A
a high-impedance state.
Test Mode
Vs. The Test Mode allows independent evaluation of the coder and
decoder. In this mode, A
IN
is internally connected to the input of the coder and its output is available on the D
pin. The output of the decoder is made available on the A
OUT
is forced to the level of AG, and D
OUT
goes into
In the Test Mode the TEST pin is connected to
OUT
OUT
pin.
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