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參數(shù)資料
| 型號(hào)： | MB6021A |
| 廠商： | Fujitsu Limited |
| 英文描述： | PCM Coders/Decoders(脈沖編碼器/解碼器) |
| 中文描述： | 的PCM編碼器/解碼器（脈沖編碼器/解碼器） |
| 文件頁數(shù)： | 3/20頁 |
| 文件大?。?/td> | 308K |
| 代理商： | MB6021A |
3
MB6021A/MB6022A
I
PIN DESCRIPTION
(Continued)
Pin No.
Pin Name
Description
1
A
IN
Analog Input
This is an input pin for analog signals to be filtered and coded.
2
3
GA1
GA2
Gain Adjust1
Gain Adjust2
These pins are provided for adjusting the gain of the Transmit Section. GA1 and
GA2 are the inverted input and output of the amplifier, respectively. GA2 can
drive a load impedance of 10 to 20 k
and 50 pF or less.
Analog Ground
All analog signals are referenced to this pin.
4
AG
5
A
OUT
Analog Output
This pin outputs the decoded and filtered analog signals. It can drive a load
impedance of 3 k
or greater, and 100 pF or less. This output is forced to AG
level in the Analog Loopback Mode and Power-down Mode.
6
TEST
Test
If this pin is at the TTL low level or left open, normal operating mode is selected.
If it is connected to–Vs, the TEST mode is selected. In TEST mode, A
internally connected to the coder input and its output is available on the D
pin. Decoder output is available on the A
exceed 2.0 V.
±
5%
Digital Input
This is a TTL-compatible input to the decoder and accepts an eight-bit data
word into the shift register on the falling edge of RCLK.
IN
is
OUT
OUT
pin. Applied voltage should not
7
+V
S
Positive Voltage Supply:
+5 V
8
D
IN
9
RCLK
Receive Clock
This TTL-compatible input defines the bit rate on the receive PCM highway. The
device can operate with bit rates of 64 kHz to 3.152 MHz. The digital PMC
codes are accepted on the falling edge of the clock.
10
XCLK
Transmit Clock
This TTL-compatible input defines the bit rate on the transmit PCM highway.
The device can operate with bit rates of 64 kHz to 3.152 MHz. The digital PCM
codes are shifted out of the digital output (D
XCLK.
OUT
) pin on the rising edge of the
11
RSYNC
Receive Synchronization Clock
This TTL-compatible input defines the beginning of the recieve time slot on the
receive PCM highway. It must be synchronized with RCLK. The clock rate is
typically 8 kHz and its duration can be equal to or more than one RCLK cycle.
12
XSYNC
Transmit Synchronization Clock
This TTL-compatible input defines the beginning of the transmit time slot on the
transmit PCM highway. It must be synchronized with XCLK. The clock rate is
typically 8 kHz and its duration can be equal to or more than one XCLK cycle.
13
DG
Digital Ground
All digital signals are referenced to this pin.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB6021A-P | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:SINGLE CHIP CODEC WITH FILTERS |
| MB6021A-PD | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:SINGLE CHIP CODEC WITH FILTERS |
| MB6022 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Product Summary Prototyping Kits |
| MB6022A | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:SINGLE CHIP CODEC WITH FILTERS |
| MB6022ABC-3 | 功能描述:麥克風(fēng) 6.0DIA X 2.2MM -45 SENS OMNI 60 S/N RoHS:否 制造商:Knowles Acoustics 方向性:Omnidirectional 阻抗:4.4 K Ohms 工作電壓:0.9 V to 10 V 靈敏度:- 53 dB 端接類型:Wire Leads 長度:5.56 mm 寬度:3.98 mm 深度:2.21 mm |
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